244 lines
9.7 KiB
C
244 lines
9.7 KiB
C
/****************************************************************************
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* boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_F091RC_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_F091RC_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* Four different clock sources can be used to drive the system clock
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* (SYSCLK):
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*
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* - HSI high-speed internal oscillator clock
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* Generated from an internal 8 MHz RC oscillator
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* - HSE high-speed external oscillator clock
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* Normally driven by an external crystal (X3). However, this crystal is
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* not fitted on the Nucleo-F091RC board.
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* - PLL clock
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* - MSI multispeed internal oscillator clock
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* The MSI clock signal is generated from an internal RC oscillator. Seven
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* frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz,
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* 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz.
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*
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* The devices have the following two secondary clock sources
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* - LSI low-speed internal RC clock
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* Drives the watchdog and RTC. Approximately 37KHz
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* - LSE low-speed external oscillator clock
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* Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
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*/
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#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
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#define STM32_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */
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#define STM32_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */
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#define STM32_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSI_FREQUENCY 40000 /* Approximately 40KHz */
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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/* PLL Configuration
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*
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* - PLL source is HSI -> 8MHz input (nominal)
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* - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output
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* - PLL multipler is 12 -> 48MHz PLL VCO clock output (for USB)
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*
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* Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz
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*
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* USB:
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* If the USB interface is used in the application, it requires a precise
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* 48MHz clock which can be generated from either the (1) the internal
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* main PLL with the HSE clock source using an HSE crystal oscillator. In
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* this case, the PLL VCO clock (defined by STM32_CFGR_PLLMUL) must be
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* programmed to output a 96 MHz frequency. This is required to provide a
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* 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal
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* 48MHz oscillator in automatic trimming mode. The synchronization for
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* this oscillator can be taken from the USB data stream itself (SOF
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* signalization) which allows crystal-less operation.
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* SYSCLK
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* The system clock is derived from the PLL VCO divided by the output
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* division factor.
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* Limitations:
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* - 96 MHz as PLLVCO when the product is in range 1 (1.8V),
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* - 48 MHz as PLLVCO when the product is in range 2 (1.5V),
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* - 24 MHz when the product is in range 3 (1.2V).
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* - Output division to avoid exceeding 32 MHz as SYSCLK.
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* - The minimum input clock frequency for PLL is 2 MHz (when using HSE as
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* PLL source).
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*/
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
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#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
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#ifdef CONFIG_STM32F0L0G0_USB
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# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
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# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
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# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
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#else
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# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
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# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
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# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
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#endif
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/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO
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* output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
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*/
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#ifdef CONFIG_STM32F0L0G0_USB
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# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
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#else
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# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
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#endif
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK (48MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (48MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */
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#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY)
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/* LED definitions **********************************************************/
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/* LEDs
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*
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* The Nucleo-64 board has one user controllable LED, User LD2. This green
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* LED is a user LED connected to Arduino signal D13 corresponding to STM32
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* I/O PA5 (PB13 on other some other Nucleo-64 boards).
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*
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* - When the I/O is HIGH value, the LED is on
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* - When the I/O is LOW, the LED is off
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LD2 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LD2_BIT (1 << BOARD_LD2)
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
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* events as follows when the red LED (PE24) is available:
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*
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* SYMBOL Meaning LD2
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* ------------------- ----------------------- -----------
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* LED_STARTED NuttX has been started OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF
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* LED_IRQSENABLED Interrupts enabled OFF
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* LED_STACKCREATED Idle stack created ON
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* LED_INIRQ In an interrupt No change
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* LED_SIGNAL In a signal handler No change
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* LED_ASSERTION An assertion failed No change
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* LED_PANIC The system has crashed Blinking
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* LED_IDLE MCU is is sleep mode Not used
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*
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* Thus if LD2, NuttX has successfully booted and is, apparently, running
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* normally. If LD2 is flashing at approximately 2Hz, then a fatal error
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* has been detected and the system has halted.
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 1
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/* Button definitions *******************************************************/
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/* Buttons
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*
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* B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
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* microcontroller.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate Pin Functions **************************************************/
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/* I2C
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* PB8 - D15
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* PB9 - D14
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*/
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#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_LOW) /* PB8 */
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#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_LOW) /* PB9 */
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/* SPI */
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#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_MEDIUM) /* D12 - PA6 */
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#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_MEDIUM) /* D11 - PA7 */
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#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_MEDIUM) /* D13 - PA5 */
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/* USART 1 */
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#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_HIGH) /* PA9 */
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#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_HIGH) /* PA10 */
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/* USART 2 */
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#define GPIO_USART2_TX (GPIO_USART2_TX_3|GPIO_SPEED_HIGH) /* PA2 */
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#define GPIO_USART2_RX (GPIO_USART2_RX_3|GPIO_SPEED_HIGH) /* PA3 */
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#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_F091RC_INCLUDE_BOARD_H */
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