317 lines
11 KiB
C
317 lines
11 KiB
C
/****************************************************************************
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* boards/arm/sam34/sam4e-ek/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAM34_SAM4E_EK_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAM34_SAM4E_EK_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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# ifdef CONFIG_SAM34_GPIO_IRQ
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# include <arch/irq.h>
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# endif
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* After power-on reset, the SAM4E16 device is running out of the Master
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* Clock using the Fast RC Oscillator running at 4 MHz.
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*
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* MAINOSC: Frequency = 12MHz (crystal)
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*
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* CONFIG_SAM4EEK_120MHZ
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* PLLA: PLL Divider = 1, Multiplier = 20 to generate PLLACK = 240MHz
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* Master Clock (MCK): Source = PLLACK,
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* Prescalar = 1 to generate MCK = 120MHz
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* CPU clock: 120MHz
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*
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* CONFIG_SAM4EEK_96MHZ
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* PLLA: PLL Divider = 1, Multiplier = 16 to generate PLLACK = 192MHz
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* Master Clock (MCK): Source = PLLACK,
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* Prescalar = 1 to generate MCK = 96MHz
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* CPU clock: 96MHz
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*/
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/* Main oscillator register settings.
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*
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* The start up time should be should be:
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* Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
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*/
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#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* PLLA configuration.
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*
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* Divider = 1
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* Multiplier = 16 or 20
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*/
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#ifdef CONFIG_SAM4EEK_120MHZ
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# define BOARD_CKGR_PLLAR_MUL (19 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#else
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# define BOARD_CKGR_PLLAR_MUL (15 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#endif
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#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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/* PMC master clock register settings.
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*
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* Source = PLLA
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* Divider = 2
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*/
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
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/* The PLL clock (USB_48M or UDPCK) is driven from the output of the PLL,
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* PLLACK. The PLL clock must be 48MHz. PLLACK can be divided down via the
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* PMC USB register to provide the PLL clock. So in order to use the USB
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* feature, the PLL output must be a multiple of 48MHz.
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*
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* PLLACK = 240MHz, USBDIV=4, USB_48M = 240 MHz / (4 + 1) = 48MHz
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* PLLACK = 192MHz, USBDIV=5, USB_48M = 192 MHz / (3 + 1) = 48MHz
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*/
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#define BOARD_PMC_USBS (0)
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#ifdef CONFIG_SAM4EEK_120MHZ
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# define BOARD_PMC_USBDIV (4 << PMC_USB_USBDIV_SHIFT)
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#else
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# define BOARD_PMC_USBDIV (3 << PMC_USB_USBDIV_SHIFT)
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#endif
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/* Resulting frequencies */
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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#ifdef CONFIG_SAM4EEK_120MHZ
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# define BOARD_PLLA_FREQUENCY (240000000) /* PLLACK: 20 * 12Mhz / 1 */
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# define BOARD_MCK_FREQUENCY (120000000) /* MCK: PLLACK / 2 */
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# define BOARD_CPU_FREQUENCY (120000000) /* CPU: MCK */
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#else
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# define BOARD_PLLA_FREQUENCY (192000000) /* PLLACK: 16 * 12Mhz / 1 */
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# define BOARD_MCK_FREQUENCY (96000000) /* MCK: PLLACK / 2 */
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# define BOARD_CPU_FREQUENCY (96000000) /* CPU: MCK */
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#endif
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV+1)).
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*
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* MCI_SPEED = MCK / (2*(CLKDIV+1))
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* CLKDIV = MCK / MCI_SPEED / 2 - 1
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*
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* Where CLKDIV has a range of 0-255.
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*/
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#ifdef CONFIG_SAM4EEK_120MHZ
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/* MCK = 120MHz, CLKDIV = 149 w/o CLKODD,
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* MCI_SPEED = 120MHz / (2*149 + 0 + 2) = 400 KHz
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*/
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# define HSMCI_INIT_CLKDIV (149 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 120MHz, CLKDIV = 2 w/o CLKODD,
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* MCI_SPEED = 120MHz / (2*2 + 0 + 2) = 20 MHz
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*/
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# define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 120MHz, CLKDIV = 1 w/ CLKODD,
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* MCI_SPEED = 120MHz / (2*1 + 1 + 2) = 24 MHz
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*/
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# define HSMCI_SDXFR_CLKDIV ((1 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)
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#else
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/* MCK = 96MHz, CLKDIV = 119, w/o CLKODD,
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* MCI_SPEED = 96MHz / (2 * 119 + 0 + 2) = 400 KHz
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*/
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# define HSMCI_INIT_CLKDIV (119 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 96MHz, CLKDIV = 1 w/ CLKODD,
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* MCI_SPEED = 96MHz / (2*1 + 1 + 2) = 19.2 MHz
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*/
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# define HSMCI_MMCXFR_CLKDIV ((3 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)
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/* MCK = 96MHz, CLKDIV = 1 w/o CLKODD,
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* MCI_SPEED = 96MHz / (2*1 + 0 + 2) = 24 MHz
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*/
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# define HSMCI_SDXFR_CLKDIV (1 << HSMCI_MR_CLKDIV_SHIFT)
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#endif
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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/* FLASH wait states.
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*
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* SAM4E-EK documentation says:
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* VDDCORE: "The voltage ranges from 1.08V to 1.32V."
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* VDDIO: Looks like it is at 3.3V
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*
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* FWS Max frequency
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* (1) (2) (3) (4)
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* --- ------- ------- ------- -------
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* 0 17 MHz 20 MHz 17 MHz 21 MHz
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* 1 34 MHz 41 MHz 35 MHz 43 MHz
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* 2 51 MHz 62 MHz 53 MHz 64 MHz
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* 3 69 MHz 83 MHz 71 MHz 86 MHz
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* 4 86 MHz 96 MHz 88 MHz 107 MHz
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* 5 100 MHz 104 MHz 106 MHz 129 MHz
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* 6 124 MHz
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* (1) VDDCORE set at 1.08V and VDDIO 1.62V to 3.6V @105C
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* (2) VDDCORE set at 1.08V and VDDIO 2.7V to 3.6V @105C
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* (3) VDDCORE set at 1.20V and VDDIO 1.62V to 3.6V @ 105C
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* (4) VDDCORE set at 1.20V and VDDIO 2.7V to 3.6V @ 105C
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*/
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#ifdef CONFIG_SAM4EEK_120MHZ
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# define BOARD_FWS 5
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#else
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# define BOARD_FWS 4
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#endif
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/* LED definitions **********************************************************/
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/* The SAM4E-EK board has three, user-controllable LEDs labelled D2 (blue),
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* D3 (amber), and D4 (green) on the board. Usage of these LEDs is defined
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* in include/board.h and src/up_leds.c. They are encoded as follows:
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*
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* SYMBOL Meaning D3* D2 D4
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* ------------------- ----------------------- ------- ------- -------
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* LED_STARTED NuttX has been started OFF OFF OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
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* LED_IRQSENABLED Interrupts enabled OFF ON OFF
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* LED_STACKCREATED Idle stack created OFF ON ON
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* LED_INIRQ In an interrupt** N/C FLASH N/C
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* LED_SIGNAL In a signal handler*** N/C N/C FLASH
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* LED_ASSERTION An assertion failed FLASH N/C N/C
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* LED_PANIC The system has crashed FLASH N/C N/C
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*
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* * If D2 and D4 are statically on, then NuttX probably failed to boot
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* and these LEDs will give you some indication of where the failure was
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* ** The normal state is D3=OFF, D4=ON and D2 faintly glowing. This faint
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* glow is because of timer interrupts that result in the LED being
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* illuminated on a small proportion of the time.
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* *** D4 may also flicker normally if signals are processed.
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*/
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#define LED_STARTED 0 /* LED0=OFF LED1=OFF LED2=OFF */
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#define LED_HEAPALLOCATE 1 /* LED0=OFF LED1=OFF LED2=ON */
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#define LED_IRQSENABLED 2 /* LED0=OFF LED1=ON LED2=OFF */
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#define LED_STACKCREATED 3 /* LED0=OFF LED1=ON LED2=ON */
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#define LED_INIRQ 4 /* LED0=XXX LED1=TOG LED2=XXX */
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#define LED_SIGNAL 5 /* LED0=XXX LED1=XXX LED2=TOG */
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#define LED_ASSERTION 6 /* LED0=TOG LED1=XXX LED2=XXX */
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#define LED_PANIC 7 /* LED0=TOG LED1=XXX LED2=XXX */
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/* LED index values for use with board_userled() */
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#define BOARD_LED_D3 0
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#define BOARD_LED_D2 1
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#define BOARD_LED_D4 2
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#define BOARD_NLEDS 3
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED_D3_BIT (1 << BOARD_LED_D3)
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#define BOARD_LED_D2_BIT (1 << BOARD_LED_D2)
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#define BOARD_LED_D4_BIT (1 << BOARD_LED_D4)
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/* Button definitions *******************************************************/
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/* Four buttons for software inputs:
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*
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* PA1 BUTTON_SCROLL-UP Grounded
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* PA2 BUTTON_SCROLL-DOWN Grounded
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* PA19 BUTTON_WAKU Grounded
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* PA20 BUTTON_TAMP Grounded
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*/
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#define BUTTON_SCROLLUP 1 /* Bit 0: Scroll-up button */
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#define BUTTON_SCROLLDOWN 2 /* Bit 1: Scroll-down button */
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#define BUTTON_WAKU 4 /* Bit 2: Waku button */
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#define BUTTON_TAMP 8 /* Bit 3: Tamp button */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: sam_lcdclear
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*
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* Description:
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* This is a non-standard LCD interface just for the SAM4e-EK board.
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* Because of the various rotations, clearing the display in the normal way
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* by writing a sequences of runs that covers the entire display can be
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* very slow.
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* Here the display is cleared by simply setting all GRAM memory to the
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* specified color.
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*
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****************************************************************************/
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#if defined(CONFIG_SAM4EEK_LCD_RGB565)
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void sam_lcdclear(uint16_t color);
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#else /* CONFIG_SAM4EEK_LCD_RGB24 || CONFIG_SAM4EEK_LCD_RGB32 */
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void sam_lcdclear(uint32_t color);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_SAM34_SAM4E_EK_INCLUDE_BOARD_H */
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