nuttx/arch/risc-v
Eero Nurkkala 8e43f39141 mpfs: cache: provide L1/L2 cache enablers
E51 may configure the L1 and L2 caches. Once configured,
no reconfiguration is possible after hardware reset is
issued.

L2 is 16-way set associative with write-back policy. The
size 2 MB, from which 1 MB is utilized with the values
provided here. That's a total of 8 ways. The rest of the
L2 is left out for the bootloader usage.

mpfs_enable_cache() first checks the bootloader usage
doesn't overlap with the cache itself, thus providing a
set of functional values.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-04 11:00:55 -03:00
..
include arch: Omni Hoverboards: update licenses to Apache 2021-09-28 04:37:38 -07:00
src mpfs: cache: provide L1/L2 cache enablers 2021-11-04 11:00:55 -03:00
Kconfig risc-v/esp32c3: Enable support for "make bootloader" target 2021-09-27 18:22:29 -07:00