8e43f39141
E51 may configure the L1 and L2 caches. Once configured, no reconfiguration is possible after hardware reset is issued. L2 is 16-way set associative with write-back policy. The size 2 MB, from which 1 MB is utilized with the values provided here. That's a total of 8 ways. The rest of the L2 is left out for the bootloader usage. mpfs_enable_cache() first checks the bootloader usage doesn't overlap with the cache itself, thus providing a set of functional values. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
165 lines
4.7 KiB
C
Executable File
165 lines
4.7 KiB
C
Executable File
/****************************************************************************
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* arch/risc-v/src/mpfs/mpfs_start.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/init.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "mpfs.h"
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#include "mpfs_clockconfig.h"
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#include "mpfs_ddr.h"
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#include "mpfs_cache.h"
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#include "mpfs_userspace.h"
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#include "riscv_arch.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_DEBUG_FEATURES
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# define showprogress(c) riscv_lowputc(c)
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#else
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# define showprogress(c)
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
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* linker script. _ebss lies at the end of the BSS region. The idle task
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* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
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* The IDLE thread is the thread that the system boots on and, eventually,
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* becomes the IDLE, do nothing task that runs only when there is nothing
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* else to run. The heap continues from there until the end of memory.
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* g_idle_topstack is a read-only variable the provides this computed
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* address.
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*/
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uintptr_t g_idle_topstack = MPFS_IDLESTACK_TOP;
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volatile bool g_serial_ok = false;
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extern void mpfs_cpu_boot(uint32_t);
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: __mpfs_start
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****************************************************************************/
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void __mpfs_start(uint32_t mhartid)
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{
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const uint32_t *src;
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uint32_t *dest;
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/* Clear .bss. We'll do this inline (vs. calling memset) just to be
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* certain that there are no issues with the state of global variables.
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*/
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for (dest = &_sbss; dest < &_ebss; )
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{
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*dest++ = 0;
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}
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/* Move the initialized data section from his temporary holding spot in
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* FLASH into the correct place in SRAM. The correct place in SRAM is
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* give by _sdata and _edata. The temporary location is in FLASH at the
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* end of all of the other read-only data (.text, .rodata) at _eronly.
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*/
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for (src = &_eronly, dest = &_sdata; dest < &_edata; )
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{
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*dest++ = *src++;
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}
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/* Setup PLL if not already provided */
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#ifdef CONFIG_MPFS_BOOTLOADER
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mpfs_clockconfig();
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#endif
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/* Configure the UART so we can get debug output */
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mpfs_lowsetup();
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showprogress('A');
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#ifdef USE_EARLYSERIALINIT
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riscv_earlyserialinit();
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#endif
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#ifdef CONFIG_MPFS_DDR_INIT
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mpfs_ddr_init();
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#endif
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showprogress('B');
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g_serial_ok = true;
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/* Do board initialization */
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mpfs_boardinitialize();
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/* Initialize the caches. Should only be executed from E51 (hart 0) to be
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* functional. Consider the caches already configured if running without
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* the CONFIG_MPFS_BOOTLOADER -option.
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*/
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#ifdef CONFIG_MPFS_BOOTLOADER
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if (mhartid == 0)
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{
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mpfs_enable_cache();
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}
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#endif
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showprogress('C');
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/* For the case of the separate user-/kernel-space build, perform whatever
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* platform specific initialization of the user memory is required.
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* Normally this just means initializing the user space .data and .bss
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* segments.
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*/
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#ifdef CONFIG_BUILD_PROTECTED
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mpfs_userspace();
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showprogress('D');
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#endif
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/* Call nx_start() */
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nx_start();
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showprogress('a');
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while (true)
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{
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asm("WFI");
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}
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}
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