Eero Nurkkala 8e43f39141 mpfs: cache: provide L1/L2 cache enablers ... E51 may configure the L1 and L2 caches. Once configured, no reconfiguration is possible after hardware reset is issued. L2 is 16-way set associative with write-back policy. The size 2 MB, from which 1 MB is utilized with the values provided here. That's a total of 8 ways. The rest of the L2 is left out for the bootloader usage. mpfs_enable_cache() first checks the bootloader usage doesn't overlap with the cache itself, thus providing a set of functional values. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>		2021-11-04 11:00:55 -03:00
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bl602/bl602evb	Open ble controller adaptation code	2021-10-08 02:30:27 -07:00
c906/smartl-c906	Rename CONFIG_LIB_BOARDCTL to CONFIG_BOARDCTL	2021-08-06 13:58:26 +02:00
esp32c3/esp32c3-devkit	esp32c3_dma: Remove the DMA test included in the driver along with its	2021-11-01 13:49:59 -05:00
fe310/hifive1-revb	Rename CONFIG_LIB_BOARDCTL to CONFIG_BOARDCTL	2021-08-06 13:58:26 +02:00
k210/maix-bit	boards: k210: Add initial gpio user space support	2021-10-17 17:29:59 +09:00
litex/arty_a7	Rename CONFIG_LIB_BOARDCTL to CONFIG_BOARDCTL	2021-08-06 13:58:26 +02:00
mpfs/icicle	mpfs: cache: provide L1/L2 cache enablers	2021-11-04 11:00:55 -03:00
rv32m1/rv32m1-vega	Rename CONFIG_LIB_BOARDCTL to CONFIG_BOARDCTL	2021-08-06 13:58:26 +02:00