ae64f28344
This is a minimalistic SBI implementation for NuttX. Provides a single service for now: - Access to machine timer Provides a start trampoline to start NuttX in S-mode: - Exceptions / faults are delegated to S-mode. - External interrupts are delegated to S-mode. Machine mode timer is used as follows: - The timer compare match register reload happens in M-mode, via call gate "riscv_sbi_set_timer" - The compare match event is dispatched to S-mode ISR, which will notify the kernel to advance time - Clearing the STIP interrupt does not work from S-mode, so the call gate does this from M-mode The only supported (tested) target for now is MPFS.
155 lines
4.3 KiB
ArmAsm
155 lines
4.3 KiB
ArmAsm
/****************************************************************************
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* arch/risc-v/src/nuttsbi/sbi_machine_trap.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include "riscv_macros.S"
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#include "riscv_internal.h"
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#include "sbi_internal.h"
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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/****************************************************************************
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* Name: machine_trap
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*
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* Description:
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* Machine mode trap handler. Handles Mtimer and simple mcall interface.
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*
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****************************************************************************/
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.section .text
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.global machine_trap
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.align 8
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machine_trap:
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/* Switch to M-mode IRQ stack */
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csrrw sp, mscratch, sp /* mscratch has user stack */
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beqz sp, .Lmtrap /* Detect recursive traps */
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addi sp, sp, -XCPTCONTEXT_SIZE
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save_ctx sp
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csrr a0, mcause /* exception cause */
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csrrw s0, mscratch, x0 /* read user stack */
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REGSTORE s0, REG_X2(sp) /* original SP */
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/* Check if this is an exception */
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bgez a0, .Lmexception
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/* Figure out which interrupt this is */
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sll a0, a0, 1 /* Shift msbit out */
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li a1, MTIMER_IRQ * 2 /* Machine timer irq ? (shifted left) */
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bne a0, a1, 1f
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/* Delegate interrupt to S-mode handler */
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li a0, MIP_MTIP
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csrc mie, a0
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li a0, MIP_STIP
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csrs mip, a0
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1:
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/* Restore mscratch */
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addi s0, sp, XCPTCONTEXT_SIZE
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csrw mscratch, s0 /* original mscratch */
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/* Restore original context */
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load_ctx sp
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REGLOAD sp, REG_SP(sp) /* restore original sp */
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/* Return from Machine Interrupt */
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mret
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.Lmexception:
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/* Handle exception, only accepted source is ecall */
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sll a0, a0, 1
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li a1, RISCV_IRQ_ECALLS * 2
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bne a0, a1, .Lmtrap
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/* Handle ecall */
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mv a0, sp
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jal x1, sbi_mcall_handle
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csrr a0, mepc
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addi a0, a0, 4
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csrw mepc, a0
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j 1b
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/* An unhandled trap to M-mode: this is an error and we cannot proceed */
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.Lmtrap:
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csrr a0, mcause /* Interrupt cause [arg0] */
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csrr a1, mepc /* Interrupt PC (instruction) [arg1] */
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jal x1, sbi_mexception
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j __start
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.Lmtraploop:
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/* If we somehow get here, prevent the software from running away */
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nop
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nop
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j .Lmtraploop
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/*****************************************************************************
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* Name: m_intstackalloc / m_intstacktop
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*
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* Description:
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* Allocate separate stack(s) for machine mode interrupts, only if kernel
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* runs in S-mode. Separate stacks are needed as M-mode interrupts can
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* pre-empt S-mode interrupts.
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*
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****************************************************************************/
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#define STACK_ALLOC_SIZE (MMODE_IRQSTACK * CONFIG_SMP_NCPUS)
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.bss
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.balign 16
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.global g_mintstackalloc
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.global g_mintstacktop
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.type g_mintstackalloc, object
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.type g_mintstacktop, object
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g_mintstackalloc:
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.skip STACK_ALIGN_UP(STACK_ALLOC_SIZE)
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g_mintstacktop:
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.size g_mintstacktop, 0
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.size g_mintstackalloc, STACK_ALIGN_DOWN(STACK_ALLOC_SIZE)
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