3a262416d6
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5146 42af7a65-404d-4744-a932-0658087f49c3
131 lines
7.3 KiB
C
131 lines
7.3 KiB
C
/************************************************************************************************
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* arch/arm/src/lpc31xx/lpc31_wdt.h
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*
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_WDT_H
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#define __ARCH_ARM_SRC_LPC31XX_LPC31_WDT_H
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/************************************************************************************************
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* Included Files
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************************************************************************************************/
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#include <nuttx/config.h>
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#include "lpc31_memorymap.h"
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/************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************************/
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/* WDT register base address offset into the APB0 domain ****************************************/
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#define LPC31_WDT_VBASE (LPC31_APB0_VADDR+LPC31_APB0_WDT_OFFSET)
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#define LPC31_WDT_PBASE (LPC31_APB0_PADDR+LPC31_APB0_WDT_OFFSET)
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/* WDT register offsets (with respect to the WDT base) ******************************************/
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#define LPC31_WDT_IR_OFFSET 0x000 /* Interrupt Register */
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#define LPC31_WDT_TCR_OFFSET 0x004 /* Timer Control Register */
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#define LPC31_WDT_TC_OFFSET 0x008 /* Timer Counter */
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#define LPC31_WDT_PR_OFFSET 0x00c /* Timer Prescale Register */
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#define LPC31_WDT_PC_OFFSET 0x010 /* Prescale Counter */
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#define LPC31_WDT_MCR_OFFSET 0x014 /* Match Control Register */
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#define LPC31_WDT_MR0_OFFSET 0x018 /* Match Register 0 */
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#define LPC31_WDT_MR1_OFFSET 0x01c /* Match Register 1 */
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/* 0x020-0x038: Reserved */
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#define LPC31_WDT_EMR_OFFSET 0x03c /* External Match Register */
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/* WDT register (virtual) addresses *************************************************************/
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#define LPC31_WDT_IR (LPC31_WDT_VBASE+LPC31_WDT_IR_OFFSET)
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#define LPC31_WDT_TCR (LPC31_WDT_VBASE+LPC31_WDT_TCR_OFFSET)
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#define LPC31_WDT_TC (LPC31_WDT_VBASE+LPC31_WDT_TC_OFFSET)
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#define LPC31_WDT_PR (LPC31_WDT_VBASE+LPC31_WDT_PR_OFFSET)
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#define LPC31_WDT_PC (LPC31_WDT_VBASE+LPC31_WDT_PC_OFFSET)
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#define LPC31_WDT_MCR (LPC31_WDT_VBASE+LPC31_WDT_MCR_OFFSET)
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#define LPC31_WDT_MR0 (LPC31_WDT_VBASE+LPC31_WDT_MR0_OFFSET)
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#define LPC31_WDT_MR1 (LPC31_WDT_VBASE+LPC31_WDT_MR1_OFFSET)
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#define LPC31_WDT_EMR (LPC31_WDT_VBASE+LPC31_WDT_EMR_OFFSET)
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/* WDT register bit definitions *****************************************************************/
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/* Interrupt Register (IR), address 0x13002400 */
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#define WDT_IR_INTRM1 (1 << 1) /* Bit 1: MR1 and TC match interrupt */
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#define WDT_IR_INTRM0 (1 << 0) /* Bit 0: MR0 and TC match interrupt */
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/* Timer Control Register (TCR), address 0x13002404 */
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#define WDT_TCR_RESET (1 << 1) /* Bit 1: Reset on the next WDOG_PCLK */
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#define WDT_TCR_ENABLE (1 << 0) /* Bit 0: Enable */
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/* Match Control Register (MCR), address 0x1300 2414 */
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#define WDT_MCR_MR1STOP (1 << 5) /* Bit 5: Stop counting when MR1=TC */
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#define WDT_MCR_MR1RESET (1 << 4) /* Bit 4: Reset TC if MR1=TC */
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#define WDT_MCR_MR1INT (1 << 3) /* Bit 3: System reset when MR1=TC */
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#define WDT_MCR_MR0STOP (1 << 2) /* Bit 2: Stop counting when MR0=TC */
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#define WDT_MCR_MR0RESET (1 << 1) /* Bit 1: Reset TC if MR0=TC */
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#define WDT_MCR_MR0INT (1 << 0) /* Bit 0: System reset when MR0=TC */
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/* External Match Registers (EMR), address 0x1300 243c */
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#define WDT_EMR_EXTMATCHCTRL1_SHIFT (6) /* Bits 6-7: Controls EXTMATCH1 when MR1=TC */
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#define WDT_EMR_EXTMATCHCTRL1_MASK (3 << WDT_EMR_EXTMATCHCTRL1_SHIFT)
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# define WDT_EMR_EXTMATCHCTRL1_NOTHING (0 << WDT_EMR_EXTMATCHCTRL1_SHIFT) /* Do Nothing */
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# define WDT_EMR_EXTMATCHCTRL1_SETLOW (1 << WDT_EMR_EXTMATCHCTRL1_SHIFT) /* Set LOW */
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# define WDT_EMR_EXTMATCHCTRL1_SETHIGH (2 << WDT_EMR_EXTMATCHCTRL1_SHIFT) /* Set HIGH */
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# define WDT_EMR_EXTMATCHCTRL1_TOGGLE (3 << WDT_EMR_EXTMATCHCTRL1_SHIFT) /* Toggle */
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#define WDT_EMR_EXTMATCHCTRL0_SHIFT (4) /* Bits 4-5: Controls EXTMATCH0 when MR0=TC */
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#define WDT_EMR_EXTMATCHCTRL0_MASK (3 << WDT_EMR_EXTMATCHCTRL0_SHIFT)
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# define WDT_EMR_EXTMATCHCTRL0_NOTHING (0 << WDT_EMR_EXTMATCHCTRL0_SHIFT) /* Do Nothing */
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# define WDT_EMR_EXTMATCHCTRL0_SETLOW (1 << WDT_EMR_EXTMATCHCTRL0_SHIFT) /* Set LOW */
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# define WDT_EMR_EXTMATCHCTRL0_SETHIGH (2 << WDT_EMR_EXTMATCHCTRL0_SHIFT) /* Set HIGH */
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# define WDT_EMR_EXTMATCHCTRL0_TOGGLE (3 << WDT_EMR_EXTMATCHCTRL0_SHIFT) /* Toggle */
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#define WDT_EMR_EXTMATCH1 (1 << 1) /* Bit 1: EXTMATCHCTRL1 controls behavior */
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#define WDT_EMR_EXTMATCH0 (1 << 0) /* Bit 0: EXTMATCHCTRL1 controls behavior */
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/************************************************************************************************
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* Public Types
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************************************************************************************************/
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/************************************************************************************************
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* Public Data
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************************************************************************************************/
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/************************************************************************************************
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* Public Functions
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************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_WDT_H */
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