224 lines
8.2 KiB
C
224 lines
8.2 KiB
C
/****************************************************************************
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* arch/avr/src/at32uc3/at32uc3_timerisr.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "avr_internal.h"
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#include "chip.h"
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#include "at32uc3.h"
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#include "at32uc3_pm.h"
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#include "at32uc3_rtc.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The desired timer interrupt frequency is normally provided by the
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* definition CLK_TCK (see include/time.h). CLK_TCK defines the desired
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* number of system clock ticks per second. That value is a user
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* configurable setting that defaults to 100 (100 ticks per second = 10 MS
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* interval).
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*
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* However, the AVR RTC does not support that default value well and so, we
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* will insist that default is over-ridden by CONFIG_USEC_PER_TICK in the
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* configuration file. Further, we will insist that CONFIG_USEC_PER_TICK
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* have the value 10000 (see reasoning below).
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*/
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#if defined(CONFIG_USEC_PER_TICK) && CONFIG_USEC_PER_TICK != 10000
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# error "Only a 100KHz system clock is supported"
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#endif
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/* The frequency of the RTC is given by:
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*
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* fRTC = fINPUT / 2**(PSEL + 1)
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*
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* Using the 32KHz (actually 32786Hz) clock, various RTC counting can
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* be obtained:
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*
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* fRTC = 32768 / 2**16 = 32768/65536 = 0.5Hz -> 2000 ms per tick
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* fRTC = 32768 / 2**15 = 32768/32768 = 1.0Hz -> 1000 ms per tick
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* fRTC = 32768 / 2**14 = 32768/16384 = 2.0Hz -> 500 ms per tick
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* fRTC = 32768 / 2**13 = 32768/8192 = 4.0Hz -> 250 ms per tick
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* fRTC = 32768 / 2**12 = 32768/4096 = 8.0Hz -> 125 ms per tick
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* fRTC = 32768 / 2**11 = 32768/2048 = 16.0Hz -> 62.5 ms per tick
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* fRTC = 32768 / 2**10 = 32768/1024 = 32.0Hz -> 31.25 ms per tick
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* fRTC = 32768 / 2**9 = 32768/512 = 64.0Hz -> 15.63 ms per tick
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* fRTC = 32768 / 2**8 = 32768/256 = 125Hz -> 7.81 ms per tick
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* fRTC = 32768 / 2**7 = 32768/128 = 250Hz -> 3.91 ms per tick
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* fRTC = 32768 / 2**6 = 32768/64 = 500Hz -> 1.95 ms per tick
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* fRTC = 32768 / 2**5 = 32768/32 = 1KHz -> 0.98 ms per tick
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* fRTC = 32768 / 2**4 = 32768/16 = 2KHz -> 488.28 us per tick
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* fRTC = 32768 / 2**3 = 32768/8 = 4KHz -> 244.14 us per tick
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* fRTC = 32768 / 2**2 = 32768/4 = 8KHz -> 122.07 us per tick
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* fRTC = 32768 / 2 = 16KHz -> 61.03 us per tick
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*
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* We'll use PSEL == 1 (fRTC == 122.07us) and we will set TOP to 81.
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* Therefore, the TOP interrupt should occur after 81+1=82 counts
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* at a rate of 122.07us x 82 = 10.01 ms
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*
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* Using the RCOSC at a nominal 115KHz, we can do he following:
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*
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* fRTC = 115000 / 2**16 = 115000/65536 = 1.754Hz -> 569.9 ms per tick
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* fRTC = 115000 / 2**15 = 115000/32768 = 3.509Hz -> 284.9 ms per tick
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* fRTC = 115000 / 2**14 = 115000/16384 = 7.019Hz -> 142.47 ms per tick
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* fRTC = 115000 / 2**13 = 115000/8192 = 14.04Hz -> 71.23 ms per tick
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* fRTC = 115000 / 2**12 = 115000/4096 = 28.08Hz -> 35.62 ms per tick
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* fRTC = 115000 / 2**11 = 115000/2048 = 56.15Hz -> 17.81 ms per tick
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* fRTC = 115000 / 2**10 = 115000/1024 = 112.3Hz -> 8.904 ms per tick
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* fRTC = 115000 / 2**9 = 115000/512 = 224.6Hz -> 4.452 ms per tick
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* fRTC = 115000 / 2**8 = 115000/256 = 449.2Hz -> 2.227 ms per tick
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* fRTC = 115000 / 2**7 = 115000/128 = 898.4Hz -> 1.113 ms per tick
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* fRTC = 115000 / 2**6 = 115000/64 = 1.796KHz -> 556.5 us per tick
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* fRTC = 115000 / 2**5 = 115000/32 = 3.594KHz -> 278.3 us per tick
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* fRTC = 115000 / 2**4 = 115000/16 = 7.188KHz -> 139.1 us per tick
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* fRTC = 115000 / 2**3 = 115000/8 = 14.38KHz -> 69.57 us per tick
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* fRTC = 115000 / 2**2 = 115000/4 = 28.75KHz -> 34.78 us per tick
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* fRTC = 115000 / 2 = 57.50KHz -> 17l.39 us per tick
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*
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* We'll use PSEL == 3 (fRTC == 69.57ns) and we will set TOP to 79.
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* Therefore, the TOP interrupt should occur after 143+1=144 counts
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* at a rate of 69.57us x 144 = 10.02 ms
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*/
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#ifdef AVR32_CLOCK_OSC32
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# define AV32_PSEL 1
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# define AV32_TOP (82-1)
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#else
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# define AV32_PSEL 2
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# define AV32_TOP (144-1)
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Function: rtc_busy
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*
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* Description:
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* Make sure that the RTC is no busy before trying to operate on it. If
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* the RTC is busy, it will discard writes to TOP, VAL, and CTRL.
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*
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****************************************************************************/
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static void rtc_waitnotbusy(void)
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{
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while ((getreg32(AVR32_RTC_CTRL) & RTC_CTRL_BUSY) != 0);
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}
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/****************************************************************************
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* Function: at32uc3_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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static int at32uc3_timerisr(int irq, uint32_t *regs, void *arg)
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{
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/* Clear the pending timer interrupt */
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putreg32(RTC_INT_TOPI, AVR32_RTC_ICR);
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/* Process timer interrupt */
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nxsched_process_timer();
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return 0;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_timer_initialize
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*
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* Description:
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* This function is called during start-up to initialize the timer
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* interrupt. NOTE: This function depends on setup of OSC32 by
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* up_clkinitialize().
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*
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****************************************************************************/
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void up_timer_initialize(void)
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{
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uint32_t regval;
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/* Enable clocking: "The clock for the RTC bus interface (CLK_RTC) is
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* generated by the Power Manager. This clock is enabled at reset, and can
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* be disabled in the Power Manager. It is recommended to disable the RTC
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* before disabling the clock, to avoid freezing the RTC in an undefined
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* state."
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*/
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#if 0
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regval = getreg32(AVR32_PM_PBAMASK);
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regval |= PM_PBAMASK_PMRTCEIC;
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putreg32(regval, AVR32_PM_PBAMASK);
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#endif
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/* Configure the RTC. Source == 32KHz OSC32 or RC OSC */
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rtc_waitnotbusy();
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#ifdef AVR32_CLOCK_OSC32
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putreg32((RTC_CTRL_CLK32 | (AV32_PSEL << RTC_CTRL_PSEL_SHIFT) |
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RTC_CTRL_CLKEN),
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AVR32_RTC_CTRL);
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#else
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putreg32(((AV32_PSEL << RTC_CTRL_PSEL_SHIFT) | RTC_CTRL_CLKEN),
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AVR32_RTC_CTRL);
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#endif
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/* Set the counter value to zero and the TOP value to AVR32_TOP
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* (see above)
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*/
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rtc_waitnotbusy();
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putreg32(AV32_TOP, AVR32_RTC_TOP);
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rtc_waitnotbusy();
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putreg32(0, AVR32_RTC_VAL);
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/* Attach the timer interrupt vector */
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irq_attach(AVR32_IRQ_RTC, (xcpt_t)at32uc3_timerisr, NULL);
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/* Enable RTC interrupts */
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putreg32(RTC_INT_TOPI, AVR32_RTC_IER);
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/* Enable the RTC */
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rtc_waitnotbusy();
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regval = getreg32(AVR32_RTC_CTRL);
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regval |= RTC_CTRL_EN;
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putreg32(regval, AVR32_RTC_CTRL);
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}
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