Ville Juven 91063e85f0 risc-v/vfork: FPU was not saved correctly ...

The FPU register saving upon vfork entry was missing.

Also added macro that tells the actual size of an FPU reg, instead
of just having a coefficient for qfpu/no-qfpu.

2022-05-20 15:59:24 +08:00

..

bl602

arch/risc-v: Remove dupped irq code from bl602

2022-01-21 00:44:43 +08:00

c906

arch/risc-v: Remove dupped irq code from c906

2022-01-21 00:44:43 +08:00

esp32c3

esp32c3: Simplify irq dispatch logic

2022-04-07 18:16:35 +02:00

fe310

arch/risc-v: Remove dupped irq code from fe310

2022-01-21 00:44:43 +08:00

k210

arch/risc-v: Remove dupped irq code from k210

2022-01-21 00:44:43 +08:00

litex

arch/risc-v/src/litex/litex_sdio: add litesdcard peripheral driver

2022-03-30 02:35:27 +08:00

mpfs

arch/risc-v: Remove dupped irq code from mpfs

2022-01-21 00:44:43 +08:00

qemu-rv

arch/risc-v: Remove dupped irq code from qemu-rv

2022-01-21 00:44:43 +08:00

rv32m1

arch/risc-v: Merge mcause.h into irq.h

2022-01-22 14:57:05 +08:00

.gitignore

…

arch.h

Revert "arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm"

2022-05-01 11:31:01 +03:00

barriers.h

RISC-V: Add common data memory and instruction barriers

2022-03-18 18:20:12 +08:00

csr.h

arch/riscv: Align the macro definition in csr.h

2022-04-02 14:08:37 +03:00

elf.h

…

inttypes.h

arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64

2022-01-04 23:22:43 +08:00

irq.h

risc-v/vfork: FPU was not saved correctly

2022-05-20 15:59:24 +08:00

limits.h

…

mode.h

arch/riscv: Access [m|s]scratch through CSR_SCRATCH macro

2022-04-02 14:08:37 +03:00

setjmp.h

arch/risc-v: Save/Load float register in setjmp

2022-03-09 10:15:54 +02:00

spinlock.h

arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64

2022-01-04 23:22:43 +08:00

stdarg.h

…

syscall.h

arch: risc-v: Add support for semihosting and hostfs

2022-05-02 19:46:58 +08:00

types.h

arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64

2022-01-04 23:22:43 +08:00