Pavel Pisa 913de5e216 arch/arm/src/lpc17xx_40xx/lpc17_40_can.c: f BOARD_CCLKSEL_DIVIDER is not equal to 1 on LPC178x or LPC40xx then base clock rate is calculated incorrectly because CCLK frequency does not correspond to PLL0 clock which is used for PCLK. This is partially workaround solution. It would be probably better to define BOARD_PCLK_FREQUENCY even for LPC176x targets and use that to replace divisor by base_clock in up_dev_s.

2019-08-13 16:16:49 -06:00

..

include

This commit brings the initial files for a port to the NXP S32K1xx family. This is very much a work in progress and is little more that a partial configuration/build environment and some S32K1xx register definition header files

2019-08-12 12:12:58 -06:00

src

arch/arm/src/lpc17xx_40xx/lpc17_40_can.c: f BOARD_CCLKSEL_DIVIDER is not equal to 1 on LPC178x or LPC40xx then base clock rate is calculated incorrectly because CCLK frequency does not correspond to PLL0 clock which is used for PCLK. This is partially workaround solution. It would be probably better to define BOARD_PCLK_FREQUENCY even for LPC176x targets and use that to replace divisor by base_clock in up_dev_s.

2019-08-13 16:16:49 -06:00

Kconfig

This commit brings the initial files for a port to the NXP S32K1xx family. This is very much a work in progress and is little more that a partial configuration/build environment and some S32K1xx register definition header files

2019-08-12 12:12:58 -06:00