d1a3f5e47f
to fix the following clang warning:
Error: chip/eoss3_irq.c:138:47: error: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Werror,-Wformat]
_err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
~~~~ ^~~~~~~~~~~~~~~~~~~~~~
%08lx
/github/workspace/sources/nuttx/include/debug.h:126:57: note: expanded from macro '_err'
__arch_syslog(LOG_ERR, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
~~~~~~ ^~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:134:24: note: expanded from macro 'getreg32'
^~~~~~~~~~~~~~~~~~~~~~~~~~~
Error: chip/eoss3_irq.c:146:49: error: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Werror,-Wformat]
_err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
~~~~ ^~~~~~~~~~~~~~~~~~~~~~
%08lx
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
673 lines
19 KiB
C
673 lines
19 KiB
C
/****************************************************************************
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* arch/arm/src/samd5e5/sam_irq.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include <arch/armv7-m/nvicpri.h>
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#include "nvic.h"
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#include "ram_vectors.h"
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#include "arm_internal.h"
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#ifdef CONFIG_SAMD5E5_EIC
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# include "sam_eic.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Get a 32-bit version of the default priority */
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#define DEFPRIORITY32 \
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(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
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NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
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NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
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NVIC_SYSH_PRIORITY_DEFAULT)
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/* Given the address of a NVIC ENABLE register, this is the offset to
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* the corresponding CLEAR ENABLE register.
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*/
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#define NVIC_ENA_OFFSET (0)
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#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: sam_dumpnvic
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*
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* Description:
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* Dump some interesting NVIC registers
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*
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****************************************************************************/
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#if defined(CONFIG_DEBUG_IRQ_INFO)
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static void sam_dumpnvic(const char *msg, int irq)
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{
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irqstate_t flags;
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flags = enter_critical_section();
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irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
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irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
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getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
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#if 0
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irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x "
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"SYSTICK: %08x\n",
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getreg32(NVIC_SYSHCON_MEMFAULTENA),
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getreg32(NVIC_SYSHCON_BUSFAULTENA),
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getreg32(NVIC_SYSHCON_USGFAULTENA),
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getreg32(NVIC_SYSTICK_CTRL_ENABLE));
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#endif
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irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
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getreg32(NVIC_IRQ0_31_ENABLE),
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getreg32(NVIC_IRQ32_63_ENABLE),
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getreg32(NVIC_IRQ64_95_ENABLE));
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#if SAM_IRQ_NEXTINT > 95
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irqinfo(" : %08x %08x %08x\n",
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getreg32(NVIC_IRQ96_127_ENABLE),
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getreg32(NVIC_IRQ128_159_ENABLE),
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getreg32(NVIC_IRQ160_191_ENABLE));
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#endif
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#if SAM_IRQ_NEXTINT > 191
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# warning Missing logic
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#endif
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irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
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getreg32(NVIC_SYSH4_7_PRIORITY),
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getreg32(NVIC_SYSH8_11_PRIORITY),
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getreg32(NVIC_SYSH12_15_PRIORITY));
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irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ0_3_PRIORITY),
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getreg32(NVIC_IRQ4_7_PRIORITY),
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getreg32(NVIC_IRQ8_11_PRIORITY),
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getreg32(NVIC_IRQ12_15_PRIORITY));
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#if SAM_IRQ_NEXTINT > 15
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ16_19_PRIORITY),
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getreg32(NVIC_IRQ20_23_PRIORITY),
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getreg32(NVIC_IRQ24_27_PRIORITY),
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getreg32(NVIC_IRQ28_31_PRIORITY));
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#endif
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#if SAM_IRQ_NEXTINT > 31
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ32_35_PRIORITY),
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getreg32(NVIC_IRQ36_39_PRIORITY),
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getreg32(NVIC_IRQ40_43_PRIORITY),
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getreg32(NVIC_IRQ44_47_PRIORITY));
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#endif
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#if SAM_IRQ_NEXTINT > 47
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ48_51_PRIORITY),
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getreg32(NVIC_IRQ52_55_PRIORITY),
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getreg32(NVIC_IRQ56_59_PRIORITY),
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getreg32(NVIC_IRQ60_63_PRIORITY));
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#endif
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#if SAM_IRQ_NEXTINT > 63
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ64_67_PRIORITY),
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getreg32(NVIC_IRQ68_71_PRIORITY),
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getreg32(NVIC_IRQ72_75_PRIORITY),
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getreg32(NVIC_IRQ76_79_PRIORITY));
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#endif
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#if SAM_IRQ_NEXTINT > 79
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ80_83_PRIORITY),
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getreg32(NVIC_IRQ84_87_PRIORITY),
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getreg32(NVIC_IRQ88_91_PRIORITY),
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getreg32(NVIC_IRQ92_95_PRIORITY));
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#endif
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#if SAM_IRQ_NEXTINT > 95
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ96_99_PRIORITY),
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getreg32(NVIC_IRQ100_103_PRIORITY),
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getreg32(NVIC_IRQ104_107_PRIORITY),
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getreg32(NVIC_IRQ108_111_PRIORITY));
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#endif
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#if SAM_IRQ_NEXTINT > 111
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ112_115_PRIORITY),
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getreg32(NVIC_IRQ116_119_PRIORITY),
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getreg32(NVIC_IRQ120_123_PRIORITY),
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getreg32(NVIC_IRQ124_127_PRIORITY));
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#endif
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#if SAM_IRQ_NEXTINT > 127
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ128_131_PRIORITY),
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getreg32(NVIC_IRQ132_135_PRIORITY),
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getreg32(NVIC_IRQ136_139_PRIORITY),
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getreg32(NVIC_IRQ140_143_PRIORITY));
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#endif
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#if SAM_IRQ_NEXTINT > 143
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# warning Missing logic
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#endif
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leave_critical_section(flags);
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}
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#else
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# define sam_dumpnvic(msg, irq)
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#endif
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/****************************************************************************
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* Name: sam_nmi, sam_pendsv, sam_dbgmonitor,
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* sam_pendsv, sam_reserved
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*
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* Description:
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* Handlers for various exceptions. None are handled and all are fatal
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* error conditions. The only advantage these provided over the default
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* unexpected interrupt handler is that they provide a diagnostic output.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_FEATURES
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static int sam_nmi(int irq, void *context, void *arg)
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{
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up_irq_save();
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_err("PANIC!!! NMI received\n");
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PANIC();
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return 0;
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}
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static int sam_pendsv(int irq, void *context, void *arg)
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{
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up_irq_save();
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_err("PANIC!!! PendSV received\n");
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PANIC();
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return 0;
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}
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static int sam_dbgmonitor(int irq, void *context, void *arg)
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{
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up_irq_save();
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_err("PANIC!!! Debug Monitor received\n");
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PANIC();
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return 0;
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}
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static int sam_reserved(int irq, void *context, void *arg)
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{
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up_irq_save();
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_err("PANIC!!! Reserved interrupt\n");
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PANIC();
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return 0;
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}
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#endif
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/****************************************************************************
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* Name: sam_prioritize_syscall
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*
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* Description:
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* Set the priority of an exception. This function may be needed
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* internally even if support for prioritized interrupts is not enabled.
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*
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****************************************************************************/
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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static inline void sam_prioritize_syscall(int priority)
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{
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uint32_t regval;
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/* SVCALL is system handler 11 */
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regval = getreg32(NVIC_SYSH8_11_PRIORITY);
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regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
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regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
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putreg32(regval, NVIC_SYSH8_11_PRIORITY);
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}
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#endif
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/****************************************************************************
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* Name: sam_irqinfo
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*
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* Description:
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* Given an IRQ number, provide the register and bit setting to enable or
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* disable the irq.
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*
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****************************************************************************/
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static int sam_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
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uintptr_t offset)
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{
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unsigned int extint = irq - SAM_IRQ_EXTINT;
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DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS);
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/* Check for external interrupt */
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if (irq >= SAM_IRQ_EXTINT)
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{
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#if SAM_IRQ_NEXTINT <= 32
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if (extint < SAM_IRQ_NEXTINT)
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{
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*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
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*bit = 1 << extint;
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}
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else
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#elif SAM_IRQ_NEXTINT <= 64
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if (extint < 32)
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{
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*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
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*bit = 1 << extint;
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}
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else if (extint < SAM_IRQ_NEXTINT)
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{
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*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
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*bit = 1 << (extint - 32);
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}
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else
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#elif SAM_IRQ_NEXTINT <= 96
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if (extint < 32)
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{
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*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
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*bit = 1 << extint;
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}
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else if (extint < 64)
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{
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*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
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*bit = 1 << (extint - 32);
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}
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else if (extint < SAM_IRQ_NEXTINT)
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{
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*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
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*bit = 1 << (extint - 64);
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}
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else
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#elif SAM_IRQ_NEXTINT <= 128
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if (extint < 32)
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{
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*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
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*bit = 1 << extint;
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}
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else if (extint < 64)
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{
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*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
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*bit = 1 << (extint - 32);
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}
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else if (extint < 96)
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{
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*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
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*bit = 1 << (extint - 64);
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}
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else if (extint < SAM_IRQ_NEXTINT)
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{
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*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
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*bit = 1 << (extint - 96);
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}
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else
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#elif SAM_IRQ_NEXTINT <= 160
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if (extint < 32)
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{
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*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
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*bit = 1 << extint;
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}
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else if (extint < 64)
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{
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*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
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*bit = 1 << (extint - 32);
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}
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else if (extint < 96)
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{
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*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
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*bit = 1 << (extint - 64);
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}
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else if (extint < 128)
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{
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*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
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*bit = 1 << (extint - 96);
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}
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else if (extint < SAM_IRQ_NEXTINT)
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{
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*regaddr = (NVIC_IRQ128_159_ENABLE + offset);
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*bit = 1 << (extint - 128);
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}
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else
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#else
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# warning Missing logic
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#endif
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{
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return ERROR; /* Invalid interrupt */
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}
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}
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/* Handle processor exceptions. Only a few can be disabled */
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else
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{
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*regaddr = NVIC_SYSHCON;
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if (irq == SAM_IRQ_MEMFAULT)
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{
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*bit = NVIC_SYSHCON_MEMFAULTENA;
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}
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else if (irq == SAM_IRQ_BUSFAULT)
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{
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*bit = NVIC_SYSHCON_BUSFAULTENA;
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}
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else if (irq == SAM_IRQ_USAGEFAULT)
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{
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*bit = NVIC_SYSHCON_USGFAULTENA;
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}
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else if (irq == SAM_IRQ_SYSTICK)
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{
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*regaddr = NVIC_SYSTICK_CTRL;
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*bit = NVIC_SYSTICK_CTRL_ENABLE;
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}
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else
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{
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return ERROR; /* Invalid or unsupported exception */
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}
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}
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_irqinitialize
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****************************************************************************/
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void up_irqinitialize(void)
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{
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uintptr_t regaddr;
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#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI)
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uint32_t regval;
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#endif
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int nintlines;
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int i;
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/* The NVIC ICTR register (bits 0-4) holds the number of interrupt
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* lines that the NVIC supports, defined in groups of 32. That is,
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* the total number of interrupt lines is up to (32*(INTLINESNUM+1)).
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*
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* 0 -> 32 interrupt lines, 1 enable register, 8 priority registers
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* 1 -> 64 " " " ", 2 enable registers, 16 priority registers
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* 2 -> 96 " " " ", 3 enable registers, 24 priority registers
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* ...
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*/
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nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1;
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/* Disable all interrupts. There are nintlines interrupt enable
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* registers.
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*/
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for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
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i > 0;
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i--, regaddr += 4)
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{
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putreg32(0xffffffff, regaddr);
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}
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/* Make sure that we are using the correct vector table. The default
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* vector address is 0x0000:0000 but if we are executing code that is
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* positioned in SRAM or in external FLASH, then we may need to reset
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* the interrupt vector so that it refers to the table in SRAM or in
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* external FLASH.
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*/
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putreg32((uint32_t)_vectors, NVIC_VECTAB);
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#ifdef CONFIG_ARCH_RAMVECTORS
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/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
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* vector table that requires special initialization.
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*/
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arm_ramvec_initialize();
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#endif
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/* Set all interrupts (and exceptions) to the default priority */
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putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
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/* Now set all of the interrupt lines to the default priority. There are
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* nintlines * 8 priority registers.
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*/
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for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY;
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i > 0;
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i--, regaddr += 4)
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{
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putreg32(DEFPRIORITY32, regaddr);
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}
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/* Attach the SVCall and Hard Fault exception handlers. The SVCall
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* exception is used for performing context switches; The Hard Fault
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* must also be caught because a SVCall may show up as a Hard Fault
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* under certain conditions.
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*/
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irq_attach(SAM_IRQ_SVCALL, arm_svcall, NULL);
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irq_attach(SAM_IRQ_HARDFAULT, arm_hardfault, NULL);
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/* Set the priority of the SVCall interrupt */
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#ifdef CONFIG_ARCH_IRQPRIO
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/* up_prioritize_irq(SAM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
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#endif
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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sam_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
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#endif
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/* If the MPU is enabled, then attach and enable the Memory Management
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* Fault handler.
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*/
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#ifdef CONFIG_ARM_MPU
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|
irq_attach(SAM_IRQ_MEMFAULT, arm_memfault, NULL);
|
|
up_enable_irq(SAM_IRQ_MEMFAULT);
|
|
#endif
|
|
|
|
/* Attach all other processor exceptions (except reset and sys tick) */
|
|
|
|
#ifdef CONFIG_DEBUG_FEATURES
|
|
irq_attach(SAM_IRQ_NMI, sam_nmi, NULL);
|
|
#ifndef CONFIG_ARM_MPU
|
|
irq_attach(SAM_IRQ_MEMFAULT, arm_memfault, NULL);
|
|
#endif
|
|
irq_attach(SAM_IRQ_BUSFAULT, arm_busfault, NULL);
|
|
irq_attach(SAM_IRQ_USAGEFAULT, arm_usagefault, NULL);
|
|
irq_attach(SAM_IRQ_PENDSV, sam_pendsv, NULL);
|
|
irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor, NULL);
|
|
irq_attach(SAM_IRQ_RESERVED, sam_reserved, NULL);
|
|
#endif
|
|
|
|
sam_dumpnvic("initial", SAM_IRQ_NIRQS);
|
|
|
|
/* If a debugger is connected, try to prevent it from catching hardfaults.
|
|
* If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal
|
|
* operation.
|
|
*/
|
|
|
|
#if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI)
|
|
regval = getreg32(NVIC_DEMCR);
|
|
regval &= ~NVIC_DEMCR_VCHARDERR;
|
|
putreg32(regval, NVIC_DEMCR);
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMD5E5_EIC
|
|
/* Initialize the external interrupt controller. */
|
|
|
|
sam_eic_initialize();
|
|
#endif
|
|
|
|
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
|
/* And finally, enable global interrupts */
|
|
|
|
up_irq_enable();
|
|
#endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_disable_irq
|
|
*
|
|
* Description:
|
|
* Disable the IRQ specified by 'irq'
|
|
*
|
|
****************************************************************************/
|
|
|
|
void up_disable_irq(int irq)
|
|
{
|
|
uintptr_t regaddr;
|
|
uint32_t regval;
|
|
uint32_t bit;
|
|
|
|
if (sam_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0)
|
|
{
|
|
/* Modify the appropriate bit in the register to disable the interrupt.
|
|
* For normal interrupts, we need to set the bit in the associated
|
|
* Interrupt Clear Enable register. For other exceptions, we need to
|
|
* clear the bit in the System Handler Control and State Register.
|
|
*/
|
|
|
|
if (irq >= SAM_IRQ_EXTINT)
|
|
{
|
|
putreg32(bit, regaddr);
|
|
}
|
|
else
|
|
{
|
|
regval = getreg32(regaddr);
|
|
regval &= ~bit;
|
|
putreg32(regval, regaddr);
|
|
}
|
|
}
|
|
|
|
#if 0 /* Might be useful in early bring-up */
|
|
sam_dumpnvic("disable", irq);
|
|
#endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_enable_irq
|
|
*
|
|
* Description:
|
|
* Enable the IRQ specified by 'irq'
|
|
*
|
|
****************************************************************************/
|
|
|
|
void up_enable_irq(int irq)
|
|
{
|
|
uintptr_t regaddr;
|
|
uint32_t regval;
|
|
uint32_t bit;
|
|
|
|
if (sam_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0)
|
|
{
|
|
/* Modify the appropriate bit in the register to enable the interrupt.
|
|
* For normal interrupts, we need to set the bit in the associated
|
|
* Interrupt Set Enable register. For other exceptions, we need to
|
|
* set the bit in the System Handler Control and State Register.
|
|
*/
|
|
|
|
if (irq >= SAM_IRQ_EXTINT)
|
|
{
|
|
putreg32(bit, regaddr);
|
|
}
|
|
else
|
|
{
|
|
regval = getreg32(regaddr);
|
|
regval |= bit;
|
|
putreg32(regval, regaddr);
|
|
}
|
|
}
|
|
|
|
#if 0 /* Might be useful in early bring-up */
|
|
sam_dumpnvic("enable", irq);
|
|
#endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: arm_ack_irq
|
|
*
|
|
* Description:
|
|
* Acknowledge the IRQ
|
|
*
|
|
****************************************************************************/
|
|
|
|
void arm_ack_irq(int irq)
|
|
{
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_prioritize_irq
|
|
*
|
|
* Description:
|
|
* Set the priority of an IRQ.
|
|
*
|
|
* Since this API is not supported on all architectures, it should be
|
|
* avoided in common implementations where possible.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_ARCH_IRQPRIO
|
|
int up_prioritize_irq(int irq, int priority)
|
|
{
|
|
uint32_t regaddr;
|
|
uint32_t regval;
|
|
int shift;
|
|
|
|
DEBUGASSERT(irq >= SAM_IRQ_MEMFAULT && irq < SAM_IRQ_NIRQS &&
|
|
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
|
|
|
if (irq < SAM_IRQ_EXTINT)
|
|
{
|
|
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
|
|
* registers (0-3 are invalid)
|
|
*/
|
|
|
|
regaddr = NVIC_SYSH_PRIORITY(irq);
|
|
irq -= 4;
|
|
}
|
|
else
|
|
{
|
|
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
|
|
|
|
irq -= SAM_IRQ_EXTINT;
|
|
regaddr = NVIC_IRQ_PRIORITY(irq);
|
|
}
|
|
|
|
regval = getreg32(regaddr);
|
|
shift = ((irq & 3) << 3);
|
|
regval &= ~(0xff << shift);
|
|
regval |= (priority << shift);
|
|
putreg32(regval, regaddr);
|
|
|
|
sam_dumpnvic("prioritize", irq);
|
|
return OK;
|
|
}
|
|
#endif
|