02b244cb6f
Sebastien Lorquet has submitted the CLA Uros Platise has submitted the CLA Gregory Nutt is the copyright holder for those files and he has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
79 lines
2.8 KiB
C
79 lines
2.8 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32_dfumode.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <unistd.h>
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#include <debug.h>
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#include <nuttx/signal.h>
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#include "stm32_dfumode.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_dfumode
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*
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* Description:
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* Reboot the part in DFU mode (GCC only).
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*
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* https://community.st.com/s/question/
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* 0D50X00009XkhAzSAJ/calling-stm32429ieval-bootloader
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*
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* REVISIT: STM32_SYSMEM_BASE is not 0x1fff000 for all STM32's. For F3's
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* The SYSMEM base is at 0x1fffd800
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*
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* REVISIT: RCC_APB2ENR_SYSCFGEN is not bit 14 for all STM32's. For F3's
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* and L15's, it is bit 0.
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*
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* REVISIT: STM32 F3's do not support the SYSCFG_MEMRMP register.
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*
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****************************************************************************/
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#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
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void stm32_dfumode(void)
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{
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#ifdef CONFIG_DEBUG_WARN
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_warn("Entering DFU mode...\n");
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nxsig_sleep(1);
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#endif
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asm("ldr r0, =0x40023844\n\t" /* RCC_APB2ENR */
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"ldr r1, =0x00004000\n\t" /* Enable SYSCFG clock */
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"str r1, [r0, #0]\n\t"
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"ldr r0, =0x40013800\n\t" /* SYSCFG_MEMRMP */
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"ldr r1, =0x00000001\n\t" /* Map ROM at zero */
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"str r1, [r0, #0]\n\t"
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"ldr r0, =0x1fff0000\n\t" /* ROM base */
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"ldr sp,[r0, #0]\n\t" /* SP @ 0 */
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"ldr r0,[r0, #4]\n\t" /* PC @ 4 */
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"bx r0\n");
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__builtin_unreachable(); /* Tell compiler we will not return */
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}
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#endif /* CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */
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