653 lines
18 KiB
C
653 lines
18 KiB
C
/****************************************************************************
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* arch/arm/src/sam34/sam_gpio.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <time.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "arm_arch.h"
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#include "chip.h"
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#include "sam_gpio.h"
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#include "sam_periphclks.h"
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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# include "hardware/sam3u_pio.h"
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#elif defined(CONFIG_ARCH_CHIP_SAM4E)
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# include "hardware/sam4e_pio.h"
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#elif defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
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# include "hardware/sam4s_pio.h"
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#else
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# error Unrecognized SAM architecture
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#ifdef CONFIG_DEBUG_GPIO_INFO
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static const char g_portchar[4] =
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{
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'A', 'B', 'C', 'D'
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};
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: sam_gpiobase
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*
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* Description:
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* Return the base address of the GPIO register set
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*
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****************************************************************************/
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static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset)
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{
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int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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return SAM_PION_BASE(port);
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}
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/****************************************************************************
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* Name: sam_gpiopin
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*
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* Description:
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* Return the base address of the GPIO register set
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*
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****************************************************************************/
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static inline int sam_gpiopin(gpio_pinset_t cfgset)
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{
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return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
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}
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/****************************************************************************
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* Name: sam_gpio_enableclk
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*
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* Description:
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* Enable clocking on the PIO port. Port clocking is required in the
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* following cases:
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*
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* - In order to read values in input pins from the port
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* - If the port supports interrupting pins
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* - If glitch filtering is enabled
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* - If necessary to read the input value on an open drain output (this
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* may be done in TWI logic to detect hangs on the I2C bus).
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* - If necessary to read the input value on peripheral pins.
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*
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****************************************************************************/
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static inline int sam_gpio_enableclk(gpio_pinset_t cfgset)
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{
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/* Enable the peripheral clock for the GPIO's port controller. */
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switch (cfgset & GPIO_PORT_MASK)
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{
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case GPIO_PORT_PIOA:
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sam_pioa_enableclk();
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break;
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case GPIO_PORT_PIOB:
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sam_piob_enableclk();
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break;
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#ifdef GPIO_PORT_PIOC
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case GPIO_PORT_PIOC:
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sam_pioc_enableclk();
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break;
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#endif
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#ifdef GPIO_PORT_PIOD
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case GPIO_PORT_PIOD:
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sam_piod_enableclk();
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break;
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#endif
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#ifdef GPIO_PORT_PIOE
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case GPIO_PORT_PIOE:
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sam_pioe_enableclk();
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break;
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#endif
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#ifdef GPIO_PORT_PIOF
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case GPIO_PORT_PIOF:
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sam_piof_enableclk();
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break;
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#endif
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default:
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return -EINVAL;
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}
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return OK;
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}
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/****************************************************************************
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* Name: sam_configinput
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*
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* Description:
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* Configure a GPIO input pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int sam_configinput(uintptr_t base, uint32_t pin,
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gpio_pinset_t cfgset)
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{
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#ifdef GPIO_HAVE_SCHMITT
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uint32_t regval;
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#endif
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/* Disable interrupts on the pin */
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putreg32(pin, base + SAM_PIO_IDR_OFFSET);
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/* Enable/disable the pull-up as requested */
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if ((cfgset & GPIO_CFG_PULLUP) != 0)
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{
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#ifdef GPIO_HAVE_PULLDOWN
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/* The pull-up on a pin can not be enabled if its pull-down is still
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* active. Therefore, we need to disable the pull-down first before
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* enabling the pull-up.
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*/
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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#endif
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putreg32(pin, base + SAM_PIO_PUER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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}
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#ifdef GPIO_HAVE_PULLDOWN
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/* Enable/disable the pull-down as requested */
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if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
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{
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/* The pull-down on a pin can not be enabled if its pull-up is still
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* active. Therefore, we need to disable the pull-up first before
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* enabling the pull-down.
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*/
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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}
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#endif
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/* Check if filtering should be enabled */
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if ((cfgset & GPIO_CFG_DEGLITCH) != 0)
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{
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putreg32(pin, base + SAM_PIO_IFER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
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}
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#ifdef GPIO_HAVE_SCHMITT
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/* Enable/disable the Schmitt trigger */
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regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET);
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if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
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{
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regval |= pin;
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}
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else
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{
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regval &= ~pin;
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}
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putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
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#endif
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/* Configure the pin as an input and enable the GPIO function */
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putreg32(pin, base + SAM_PIO_ODR_OFFSET);
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putreg32(pin, base + SAM_PIO_PER_OFFSET);
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/* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
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* IFDGSR registers. This would probably best be done with
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* another, new API... perhaps sam_configfilter()
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*/
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/* Enable the peripheral clock for the GPIO's port controller.
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* A GPIO input value is only sampled if the peripheral clock for its
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* controller is enabled.
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*/
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return sam_gpio_enableclk(cfgset);
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}
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/****************************************************************************
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* Name: sam_configoutput
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*
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* Description:
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* Configure a GPIO output pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int sam_configoutput(uintptr_t base, uint32_t pin,
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gpio_pinset_t cfgset)
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{
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/* Disable interrupts on the pin */
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putreg32(pin, base + SAM_PIO_IDR_OFFSET);
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/* Enable/disable the pull-up as requested */
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if ((cfgset & GPIO_CFG_PULLUP) != 0)
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{
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#ifdef GPIO_HAVE_PULLDOWN
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/* The pull-up on a pin can not be enabled if its pull-down is still
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* active. Therefore, we need to disable the pull-down first before
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* enabling the pull-up.
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*/
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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#endif
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putreg32(pin, base + SAM_PIO_PUER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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}
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#ifdef GPIO_HAVE_PULLDOWN
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/* Enable/disable the pull-down as requested */
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if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
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{
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/* The pull-down on a pin can not be enabled if its pull-up is still
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* active. Therefore, we need to disable the pull-up first before
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* enabling the pull-down.
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*/
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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}
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#endif
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/* Enable the open drain driver if requested */
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if ((cfgset & GPIO_CFG_OPENDRAIN) != 0)
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{
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putreg32(pin, base + SAM_PIO_MDER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_MDDR_OFFSET);
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}
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/* Set default value */
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if ((cfgset & GPIO_OUTPUT_SET) != 0)
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{
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putreg32(pin, base + SAM_PIO_SODR_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_CODR_OFFSET);
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}
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/* Configure the pin as an output and enable the GPIO function */
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putreg32(pin, base + SAM_PIO_OER_OFFSET);
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putreg32(pin, base + SAM_PIO_PER_OFFSET);
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return OK;
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}
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/****************************************************************************
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* Name: sam_configperiph
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*
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* Description:
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* Configure a GPIO pin driven by a peripheral A or B signal based on
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* bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int sam_configperiph(uintptr_t base, uint32_t pin,
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gpio_pinset_t cfgset)
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{
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uint32_t regval;
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/* Disable interrupts on the pin */
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putreg32(pin, base + SAM_PIO_IDR_OFFSET);
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/* Enable/disable the pull-up as requested */
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if ((cfgset & GPIO_CFG_PULLUP) != 0)
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{
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#ifdef GPIO_HAVE_PULLDOWN
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/* The pull-up on a pin can not be enabled if its pull-down is still
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* active. Therefore, we need to disable the pull-down first before
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* enabling the pull-up.
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*/
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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#endif
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putreg32(pin, base + SAM_PIO_PUER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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}
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#ifdef GPIO_HAVE_PULLDOWN
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/* Enable/disable the pull-down as requested */
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if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
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{
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/* The pull-down on a pin can not be enabled if its pull-up is still
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* active. Therefore, we need to disable the pull-up first before
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* enabling the pull-down.
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*/
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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}
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#endif
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#ifdef GPIO_HAVE_PERIPHCD
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/* Configure pin, depending upon the peripheral A, B, C or D
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*
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* PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0
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* PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0
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* PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1
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* PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1
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*/
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regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET);
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if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
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(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC)
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{
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regval &= ~pin;
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}
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else
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{
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regval |= pin;
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}
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putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET);
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regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET);
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if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
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(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB)
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{
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regval &= ~pin;
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}
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else
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{
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regval |= pin;
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}
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putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET);
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#else
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/* Configure pin, depending upon the peripheral A or B:
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*
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* PERIPHA: ABSR[n] = 0
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* PERIPHB: ABSR[n] = 1
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*/
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regval = getreg32(base + SAM_PIO_ABSR_OFFSET);
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if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA)
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{
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regval &= ~pin;
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}
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else
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{
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regval |= pin;
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}
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putreg32(regval, base + SAM_PIO_ABSR_OFFSET);
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#endif
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/* Disable PIO functionality */
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putreg32(pin, base + SAM_PIO_PDR_OFFSET);
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: sam_configgpio
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*
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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int sam_configgpio(gpio_pinset_t cfgset)
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{
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uintptr_t base = sam_gpiobase(cfgset);
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uint32_t pin = sam_gpiopin(cfgset);
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irqstate_t flags;
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int ret;
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/* Disable interrupts to prohibit re-entrance. */
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flags = enter_critical_section();
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/* Enable writing to GPIO registers */
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putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
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/* Handle the pin configuration according to pin type */
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switch (cfgset & GPIO_MODE_MASK)
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{
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case GPIO_INPUT:
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ret = sam_configinput(base, pin, cfgset);
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break;
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case GPIO_OUTPUT:
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ret = sam_configoutput(base, pin, cfgset);
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break;
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case GPIO_PERIPHA:
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case GPIO_PERIPHB:
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#ifdef GPIO_HAVE_PERIPHCD
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case GPIO_PERIPHC:
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case GPIO_PERIPHD:
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#endif
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ret = sam_configperiph(base, pin, cfgset);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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/* Disable writing to GPIO registers */
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putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
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leave_critical_section(flags);
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return ret;
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}
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/****************************************************************************
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* Name: sam_gpiowrite
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*
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* Description:
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* Write one or zero to the selected GPIO pin
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*
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****************************************************************************/
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void sam_gpiowrite(gpio_pinset_t pinset, bool value)
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{
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uintptr_t base = sam_gpiobase(pinset);
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uint32_t pin = sam_gpiopin(pinset);
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if (value)
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{
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putreg32(pin, base + SAM_PIO_SODR_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_CODR_OFFSET);
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}
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}
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/****************************************************************************
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* Name: sam_gpioread
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*
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* Description:
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* Read one or zero from the selected GPIO pin
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*
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****************************************************************************/
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bool sam_gpioread(gpio_pinset_t pinset)
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{
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uintptr_t base = sam_gpiobase(pinset);
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uint32_t pin = sam_gpiopin(pinset);
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uint32_t regval;
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if ((pinset & GPIO_MODE_MASK) == GPIO_OUTPUT)
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{
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regval = getreg32(base + SAM_PIO_ODSR_OFFSET);
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}
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else
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{
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regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
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}
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return (regval & pin) != 0;
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}
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/****************************************************************************
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* Function: sam_dumpgpio
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*
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* Description:
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* Dump all GPIO registers associated with the base address of the provided
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* pinset.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_GPIO_INFO
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int sam_dumpgpio(uint32_t pinset, const char *msg)
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{
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irqstate_t flags;
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uintptr_t base;
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unsigned int port;
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/* Get the base address associated with the PIO port */
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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base = SAM_PION_BASE(port);
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/* The following requires exclusive access to the GPIO registers */
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flags = enter_critical_section();
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gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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gpioinfo(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n",
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getreg32(base + SAM_PIO_PSR_OFFSET),
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getreg32(base + SAM_PIO_OSR_OFFSET),
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getreg32(base + SAM_PIO_IFSR_OFFSET),
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getreg32(base + SAM_PIO_ODSR_OFFSET));
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gpioinfo(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
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getreg32(base + SAM_PIO_PDSR_OFFSET),
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getreg32(base + SAM_PIO_IMR_OFFSET),
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getreg32(base + SAM_PIO_ISR_OFFSET),
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getreg32(base + SAM_PIO_MDSR_OFFSET));
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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gpioinfo(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n",
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getreg32(base + SAM_PIO_ABSR_OFFSET),
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getreg32(base + SAM_PIO_SCIFSR_OFFSET),
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getreg32(base + SAM_PIO_DIFSR_OFFSET),
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getreg32(base + SAM_PIO_IFDGSR_OFFSET));
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#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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gpioinfo(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
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getreg32(base + SAM_PIO_ABCDSR1_OFFSET),
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getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
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getreg32(base + SAM_PIO_IFSCSR_OFFSET),
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getreg32(base + SAM_PIO_PPDSR_OFFSET));
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#endif
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gpioinfo(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
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getreg32(base + SAM_PIO_PUSR_OFFSET),
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getreg32(base + SAM_PIO_SCDR_OFFSET),
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getreg32(base + SAM_PIO_OWSR_OFFSET),
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getreg32(base + SAM_PIO_AIMMR_OFFSET));
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gpioinfo(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
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getreg32(base + SAM_PIO_ESR_OFFSET),
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getreg32(base + SAM_PIO_LSR_OFFSET),
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getreg32(base + SAM_PIO_ELSR_OFFSET),
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getreg32(base + SAM_PIO_FELLSR_OFFSET));
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gpioinfo(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
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getreg32(base + SAM_PIO_FRLHSR_OFFSET),
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getreg32(base + SAM_PIO_LOCKSR_OFFSET),
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getreg32(base + SAM_PIO_WPMR_OFFSET),
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getreg32(base + SAM_PIO_WPSR_OFFSET));
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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gpioinfo(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
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getreg32(base + SAM_PIO_PCMR_OFFSET),
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getreg32(base + SAM_PIO_PCIMR_OFFSET),
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getreg32(base + SAM_PIO_PCISR_OFFSET),
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getreg32(base + SAM_PIO_PCRHR_OFFSET));
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#ifdef CONFIG_ARCH_CHIP_SAM4E
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gpioinfo("SCHMITT: %08x DELAYR:%08x\n",
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getreg32(base + SAM_PIO_SCHMITT_OFFSET),
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getreg32(base + SAM_PIO_DELAYR_OFFSET));
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#else
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gpioinfo("SCHMITT: %08x\n",
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getreg32(base + SAM_PIO_SCHMITT_OFFSET));
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#endif
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#endif
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leave_critical_section(flags);
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return OK;
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}
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#endif
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