36df84c843
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5145 42af7a65-404d-4744-a932-0658087f49c3
252 lines
8.6 KiB
C
252 lines
8.6 KiB
C
/***************************************************************************
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* z16f/z16f_clkinit.c
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*
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* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Based upon sample code included with the Zilog ZDS-II toolchain.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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/***************************************************************************
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* Included Files
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***************************************************************************/
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#include "chip/chip.h"
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/***************************************************************************
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* Definitions
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***************************************************************************/
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/* System clock source value from ZDS target settings */
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extern _Erom unsigned long SYS_CLK_SRC;
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#define _DEFSRC ((unsigned long)&SYS_CLK_SRC)
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/* System clock frequency value from ZDS target settings */
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extern _Erom unsigned long SYS_CLK_FREQ;
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#define _DEFCLK ((unsigned long)&SYS_CLK_FREQ)
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/* Setup FLASH options at address 0x00000000 */
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#if 0 /* Setup in z16f_head.S */
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Z16F_FLOPTION0 = (Z16F_FLOPTION0_MAXPWR|Z16F_FLOPTION0_WDTRES|\
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Z16F_FLOPTION0_WDTA0|Z16F_FLOPTION0_VBOA0|\
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Z16F_FLOPTION0_DBGUART|Z16F_FLOPTION0_FWP|\
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Z16F_FLOPTION0_RP);
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Z16F_FLOPTION1 = (Z16F_FLOPTION1_RESVD|Z16F_FLOPTION1_MCEN|\
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Z16F_FLOPTION1_OFFH|Z16F_FLOPTION1_OFFL);
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Z16F_FLOPTION2 = Z16F_FLOPTION2_RESVD;
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Z16F_FLOPTION3 = (Z16F_FLOPTION3_RESVD|Z16F_FLOPTION3_NORMAL);
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#endif
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/***************************************************************************
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* Private Functions
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***************************************************************************/
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#ifdef CONFIG_DEBUG
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/***************************************************************************
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* System clock initialization--DEBUG. Code Using Frequency Input from
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* ZDS IDE.
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*
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* The sysclk_init function below uses the flexibility of the ZDS debug
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* environment to allow the user to experiment with different clock frequency
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* settings to help determine the frequency requirements of his Project. The
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* function allows the selection of internal 5.56 MHz, the 10 KHz Watch Dog
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* timer or an external clock Source. ZNEO supports clock frequency division
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* with the Clock Division Register. The clock division Register will divide
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* by (a minimum of) 2 or more. An assumed clock value of 5.5 MHz internal or
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* an external clock of 20 MHz was used as the crystal frequency to match the
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* Demo Target. The User can enter a new frequency in the OTHER clock dialog
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* Target Setting. The clock frequency is passed with the variable _DEFFREQ
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* and the clock source is _DEFSRC.
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*
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* NOTE: The UART output is designed to work with 5.56 MHz internal and 20 MHz
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* External clock frequencies at the Default Baud rate of 57.6K Baud.
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* Entering different clock frequencies may cause the UART to stop transmitting
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* unless the user makes changes to the UART routines.
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*
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* Function Not Recommended for Release Code.
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*
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***************************************************************************/
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static void z16f_sysclkinit(void)
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{
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int count;
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int temp_oscdiv;
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/* _DEFSRC (SCKSEL Bits 1,0) is passed to program view the .linkcmd file */
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if ((getreg8(Z16F_OSC_CTL) & 0x03) != _DEFSRC)
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{
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if (_DEFSRC == 0)
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{
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/* Enable 5.6 MHz clock RESET DEFAULT*/
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putreg8(0xe7, Z16F_OSC_CTL);
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putreg8(0x18, Z16F_OSC_CTL);
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putreg8(0xa0, Z16F_OSC_CTL);
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/* Wait for oscillator to stabilize */
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for (count = 0; count < 10000; count++);
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/* Select 5.6 MHz clock (SCKSEL=0) */
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putreg8(0xe7, Z16F_OSC_CTL);
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putreg8(0x18, Z16F_OSC_CTL);
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putreg8(0xa0, Z16F_OSC_CTL);
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}
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else if (_DEFSRC == 1)
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{
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/* Enable (reserved) clock */
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}
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else if (_DEFSRC == 2 )
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{
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/* Enable external oscillator */
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putreg8(0xe7, Z16F_OSC_CTL);
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putreg8(0x18, Z16F_OSC_CTL);
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putreg8(0xe0, Z16F_OSC_CTL);
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/* Wait for oscillator to stabilize */
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for (count = 0; count < 10000; count++);
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/* select external oscillator (SCKSEL=2) */
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putreg8(0xe7, Z16F_OSC_CTL);
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putreg8(0x18, Z16F_OSC_CTL);
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putreg8(0xe0 | 2, Z16F_OSC_CTL);
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}
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else if (_DEFSRC == 3)
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{
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/* Enable watchdog timer clock */
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putreg8(0xe7, Z16F_OSC_CTL);
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putreg8(0x18, Z16F_OSC_CTL);
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putreg8(0xb0, Z16F_OSC_CTL);
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/* Wait for oscillator to stabilize */
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for (count = 0; count < 10000; count++);
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/* Select watch dog timer clock (SKCSEL=3) */
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putreg8(0xe7, Z16F_OSC_CTL);
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putreg8(0x18, Z16F_OSC_CTL);
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putreg8(0xb0 | 3, Z16F_OSC_CTL);
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}
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}
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/* Check SysClock Frequency.
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* divide the clock if the user has selected the OTHER option for frequency.
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*/
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if (((_DEFSRC == 0) && (_DEFCLK < 3000000ul)) ||
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((_DEFSRC == 2) && (_DEFCLK <= 10000000ul)))
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{
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if ( _DEFSRC == 0 )
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{
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temp_oscdiv = ( 5526000ul / (_DEFCLK +1) );
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/* Example @ 32 KHz: 0xAC (172 decimal)*/
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}
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else
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{
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temp_oscdiv = (( 20000000ul / (_DEFCLK +1) ) + 1 );
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}
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/* Unlock and Set the Oscillator Division Register (Z16F_OSC_DIV) */
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putreg8(0xE7, Z16F_OSC_CTL);
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putreg8(0x18, Z16F_OSC_CTL);
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putreg8(temp_oscdiv, Z16F_OSC_DIV);
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}
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/* Wait for oscillator to stabilize */
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for (count = 0; count < 10000; count++);
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}
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#else /* CONFIG_DEBUG */
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/***************************************************************************
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* System Clock Initialization Recommended for Release Code
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*
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* The z16f_sysclkinit function below allows the user to switch from
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* Internal to External Clock source and should be used for clock frequency
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* switching to the External Clock. Note the delay to allow the clock to
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* stabilize.
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***************************************************************************/
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static void z16f_sysclkinit(void)
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{
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int count;
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/*
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* _DEFSRC (SCKSEL Bits 1,0) is passed to program from Target Settings Dialog.
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* I.E. extern _Erom unsigned long SYS_CLK_SRC;
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*/
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if ((getreg8(Z16F_OSC_CTL) & 0x03) != _DEFSRC)
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{
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/* Enable external oscillator */
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putreg8(0xe7, Z16F_OSC_CTL);
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putreg8(0x18, Z16F_OSC_CTL);
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putreg8(0xe0, Z16F_OSC_CTL);
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/* Wait for oscillator to stabilize */
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for (count = 0; count < 10000; count++);
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/* Select external oscillator (SCLKSEL=2) */
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putreg8(0xe7, Z16F_OSC_CTL);
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putreg8(0x18, Z16F_OSC_CTL);
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putreg8(0xe0 | 2, Z16F_OSC_CTL);
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}
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}
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#endif /* CONFIG_DEBUG */
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/***************************************************************************
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* Public Functions
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***************************************************************************/
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/***************************************************************************
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* Name: z16f_clkinit
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***************************************************************************/
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void z16f_clkinit(void)
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{
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z16f_sysclkinit();
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}
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