4fbe424050
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3119 42af7a65-404d-4744-a932-0658087f49c3
352 lines
15 KiB
ArmAsm
Executable File
352 lines
15 KiB
ArmAsm
Executable File
/************************************************************************************************
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* arch/arm/src/lpc17xx/lpc17_vectors.S
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* arch/arm/src/chip/lpc17_vectors.S
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************/
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/************************************************************************************************
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* Included Files
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************************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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/************************************************************************************************
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* Preprocessor Definitions
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************************************************************************************************/
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/* Memory Map:
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*
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* 0x0000:0000 - Beginning of FLASH. Address of vectors
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* 0x0003:ffff - End of flash
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* 0x1000:0000 - Start of CPU SRAM and start of .data (_sdata)
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* - End of .data (_edata) and start of .bss (_sbss)
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* - End of .bss (_ebss) and bottom of idle stack
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* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap. NOTE
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* that the ARM uses a decrement before store stack so that the correct initial
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* value is the end of the stack + 4;
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* 0x1000:7fff - End of CPU SRAM and end of heap (1st region)
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*/
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#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
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#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
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/* The Cortex-M3 return from interrupt is unusual. We provide the following special
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* address to the BX instruction. The particular value also forces a return to
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* thread mode and covers state from the main stack point, the MSP (vs. the MSP).
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*/
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#define EXC_RETURN 0xfffffff9
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/************************************************************************************************
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* Global Symbols
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************************************************************************************************/
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.globl __start
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.syntax unified
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.thumb
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.file "lpc17_vectors.S"
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/************************************************************************************************
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* Macros
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************************************************************************************************/
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/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3
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* registers on the stack, then branches to an instantantiation of the following
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* macro. This macro simply loads the IRQ number into R0, then jumps to the common
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* IRQ handling logic.
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*/
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.macro HANDLER, label, irqno
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.thumb_func
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\label:
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mov r0, #\irqno
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b lpc17_common
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.endm
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/************************************************************************************************
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* Vectors
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************************************************************************************************/
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.section .vectors, "ax"
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.code 16
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.align 2
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.globl lpc17_vectors
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.type lpc17_vectors, function
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lpc17_vectors:
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/* Processor Exceptions */
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.word IDLE_STACK /* Vector 0: Reset stack pointer */
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.word __start /* Vector 1: Reset vector */
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.word lpc17_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */
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.word lpc17_hardfault /* Vector 3: Hard fault */
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.word lpc17_mpu /* Vector 4: Memory management (MPU) */
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.word lpc17_busfault /* Vector 5: Bus fault */
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.word lpc17_usagefault /* Vector 6: Usage fault */
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.word lpc17_reserved /* Vector 7: Reserved */
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.word lpc17_reserved /* Vector 8: Reserved */
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.word lpc17_reserved /* Vector 9: Reserved */
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.word lpc17_reserved /* Vector 10: Reserved */
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.word lpc17_svcall /* Vector 11: SVC call */
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.word lpc17_dbgmonitor /* Vector 12: Debug monitor */
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.word lpc17_reserved /* Vector 13: Reserved */
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.word lpc17_pendsv /* Vector 14: Pendable system service request */
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.word lpc17_systick /* Vector 15: System tick */
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/* External Interrupts */
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.word lpc17_wdt /* Vector 16+0: Watchdog timer */
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.word lpc17_tmr0 /* Vector 16+1: Timer 0 */
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.word lpc17_tmr1 /* Vector 16+2: Timer 1 */
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.word lpc17_tmr2 /* Vector 16+3: Timer 2 */
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.word lpc17_tmr3 /* Vector 16+4: Timer 3 */
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.word lpc17_uart0 /* Vector 16+5: UART 0 */
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.word lpc17_uart1 /* Vector 16+6: UART 1 */
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.word lpc17_uart2 /* Vector 16+7: UART 2 */
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.word lpc17_uart3 /* Vector 16+8: UART 3 */
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.word lpc17_pwm1 /* Vector 16+9: PWM */
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.word lpc17_i2c0 /* Vector 16+10: I2C 0 */
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.word lpc17_i2c1 /* Vector 16+11: I2C 1 */
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.word lpc17_i2c2 /* Vector 16+12: I2C 2 */
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.word lpc17_spif /* Vector 16+13: SPI */
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.word lpc17_ssp0 /* Vector 16+14: SSP 0 */
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.word lpc17_ssp1 /* Vector 16+15: SSP 1 */
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.word lpc17_pll0 /* Vector 16+16: PLL 0 */
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.word lpc17_rtc /* Vector 16+17: Real time clock */
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.word lpc17_eint0 /* Vector 16+18: External interrupt 0 */
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.word lpc17_eint1 /* Vector 16+19: External interrupt 1 */
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.word lpc17_eint2 /* Vector 16+20: External interrupt 2 */
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.word lpc17_eint3 /* Vector 16+21: External interrupt 3 */
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.word lpc17_adc /* Vector 16+22: A/D Converter */
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.word lpc17_bod /* Vector 16+23: Brown Out detect */
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.word lpc17_usb /* Vector 16+24: USB */
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.word lpc17_can /* Vector 16+25: CAN */
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.word lpc17_gpdma /* Vector 16+26: GPDMA */
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.word lpc17_i2s /* Vector 16+27: I2S */
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.word lpc17_eth /* Vector 16+28: Ethernet */
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.word lpc17_ritint /* Vector 16+29: Repetitive Interrupt Timer */
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.word lpc17_mcpwm /* Vector 16+30: Motor Control PWM */
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.word lpc17_qei /* Vector 16+31: Quadrature Encoder */
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.word lpc17_pll1 /* Vector 16+32: PLL 1 */
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.word lpc17_usbact /* Vector 16+33: USB Activity Interrupt */
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.word lpc17_canact /* Vector 16+34: CAN Activity Interrupt */
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.size lpc17_vectors, .-lpc17_vectors
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/************************************************************************************************
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* .text
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************************************************************************************************/
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.text
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.type handlers, function
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.thumb_func
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handlers:
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HANDLER lpc17_reserved, LPC17_IRQ_RESERVED /* Unexpected/reserved vector */
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HANDLER lpc17_nmi, LPC17_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
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HANDLER lpc17_hardfault, LPC17_IRQ_HARDFAULT /* Vector 3: Hard fault */
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HANDLER lpc17_mpu, LPC17_IRQ_MPU /* Vector 4: Memory management (MPU) */
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HANDLER lpc17_busfault, LPC17_IRQ_BUSFAULT /* Vector 5: Bus fault */
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HANDLER lpc17_usagefault, LPC17_IRQ_USAGEFAULT /* Vector 6: Usage fault */
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HANDLER lpc17_svcall, LPC17_IRQ_SVCALL /* Vector 11: SVC call */
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HANDLER lpc17_dbgmonitor, LPC17_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
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HANDLER lpc17_pendsv, LPC17_IRQ_PENDSV /* Vector 14: Penable system service request */
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HANDLER lpc17_systick, LPC17_IRQ_SYSTICK /* Vector 15: System tick */
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HANDLER lpc17_wdt, LPC17_IRQ_WDT /* Vector 16+0: Watchdog timer */
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HANDLER lpc17_tmr0, LPC17_IRQ_TMR0 /* Vector 16+1: Timer 0 */
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HANDLER lpc17_tmr1, LPC17_IRQ_TMR1 /* Vector 16+2: Timer 1 */
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HANDLER lpc17_tmr2, LPC17_IRQ_TMR2 /* Vector 16+3: Timer 2 */
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HANDLER lpc17_tmr3, LPC17_IRQ_TMR3 /* Vector 16+4: Timer 3 */
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HANDLER lpc17_uart0, LPC17_IRQ_UART0 /* Vector 16+5: UART 0 */
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HANDLER lpc17_uart1, LPC17_IRQ_UART1 /* Vector 16+6: UART 1 */
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HANDLER lpc17_uart2, LPC17_IRQ_UART2 /* Vector 16+7: UART 2 */
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HANDLER lpc17_uart3, LPC17_IRQ_UART3 /* Vector 16+8: UART 3 */
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HANDLER lpc17_pwm1, LPC17_IRQ_PWM1 /* Vector 16+9: PWM 1 */
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HANDLER lpc17_i2c0, LPC17_IRQ_I2C0 /* Vector 16+10: I2C 0 */
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HANDLER lpc17_i2c1, LPC17_IRQ_I2C1 /* Vector 16+11: I2C 1 */
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HANDLER lpc17_i2c2, LPC17_IRQ_I2C2 /* Vector 16+12: I2C 2 */
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HANDLER lpc17_spif, LPC17_IRQ_SPIF /* Vector 16+13: SPI */
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HANDLER lpc17_ssp0, LPC17_IRQ_SSP0 /* Vector 16+14: SSP 0 */
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HANDLER lpc17_ssp1, LPC17_IRQ_SSP1 /* Vector 16+15: SSP 1 */
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HANDLER lpc17_pll0, LPC17_IRQ_PLL0 /* Vector 16+16: PLL 0 */
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HANDLER lpc17_rtc, LPC17_IRQ_RTC /* Vector 16+17: Real time clock */
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HANDLER lpc17_eint0, LPC17_IRQ_EINT0 /* Vector 16+18: External interrupt 0 */
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HANDLER lpc17_eint1, LPC17_IRQ_EINT1 /* Vector 16+19: External interrupt 1 */
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HANDLER lpc17_eint2, LPC17_IRQ_EINT2 /* Vector 16+20: External interrupt 2 */
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HANDLER lpc17_eint3, LPC17_IRQ_EINT3 /* Vector 16+21: External interrupt 3 */
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HANDLER lpc17_adc, LPC17_IRQ_ADC /* Vector 16+22: A/D Converter */
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HANDLER lpc17_bod, LPC17_IRQ_BOD /* Vector 16+23: Brown Out detect */
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HANDLER lpc17_usb, LPC17_IRQ_USB /* Vector 16+24: USB */
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HANDLER lpc17_can, LPC17_IRQ_CAN /* Vector 16+25: CAN */
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HANDLER lpc17_gpdma, LPC17_IRQ_GPDMA /* Vector 16+26: GPDMA */
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HANDLER lpc17_i2s, LPC17_IRQ_I2S /* Vector 16+27: I2S */
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HANDLER lpc17_eth, LPC17_IRQ_ETH /* Vector 16+28: Ethernet */
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HANDLER lpc17_ritint, LPC17_IRQ_RITINT /* Vector 16+29: Repetitive Interrupt Timer */
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HANDLER lpc17_mcpwm, LPC17_IRQ_MCPWM /* Vector 16+30: Motor Control PWM */
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HANDLER lpc17_qei, LPC17_IRQ_QEI /* Vector 16+31: Quadrature Encoder */
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HANDLER lpc17_pll1, LPC17_IRQ_PLL1 /* Vector 16+32: PLL 1 */
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HANDLER lpc17_usbact, LPC17_IRQ_USBACT /* Vector 16+33: USB Activity Interrupt */
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HANDLER lpc17_canact, LPC17_IRQ_CANACT /* Vector 16+34: CAN Activity Interrupt */
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/* Common IRQ handling logic. On entry here, the stack is like the following:
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*
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* REG_XPSR
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* REG_R15
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* REG_R14
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* REG_R12
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* REG_R3
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* REG_R2
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* REG_R1
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* MSP->REG_R0
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*
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* and R0 contains the IRQ number
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*/
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lpc17_common:
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/* Complete the context save */
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mrs r1, msp /* R1=The main stack pointer */
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mov r2, r1 /* R2=Copy of the main stack pointer */
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add r2, #HW_XCPT_SIZE /* R2=MSP before the interrupt was taken */
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mrs r3, primask /* R3=Current PRIMASK setting */
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stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */
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/* Disable interrupts, select the stack to use for interrupt handling
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* and call up_doirq to handle the interrupt
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*/
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cpsid i /* Disable further interrupts */
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
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* stack pointer. The way that this is done here prohibits nested interrupts!
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* Otherwise, we will re-use the main stack for interrupt level processing.
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*/
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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ldr sp, =g_intstackbase
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str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */
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bl up_doirq /* R0=IRQ, R1=register save (msp) */
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ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */
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#else
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mov sp, r1 /* We are using the main stack pointer */
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bl up_doirq /* R0=IRQ, R1=register save (msp) */
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mov r1, sp /* Recover R1=main stack pointer */
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#endif
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/* On return from up_doirq, R0 will hold a pointer to register context
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* array to use for the interrupt return. If that return value is the same
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* as current stack pointer, then things are relatively easy.
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*/
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cmp r0, r1 /* Context switch? */
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beq 1f /* Branch if no context switch */
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/* We are returning with a pending context switch. This case is different
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* because in this case, the register save structure does not lie on the
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* stack but, rather, are within a TCB structure. We'll have to copy some
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* values to the stack.
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*/
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add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */
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ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */
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ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */
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stmdb r1!, {r4-r11} /* Store eight registers in HW save area */
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ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */
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b 2f /* Re-join common logic */
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/* We are returning with no context switch. We simply need to "unwind"
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* the same stack frame that we created
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*/
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1:
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ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */
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2:
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msr msp, r1 /* Recover the return MSP value */
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/* Restore the interrupt state. Preload r14 with the special return
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* value first (so that the return actually occurs with interrupts
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* still disabled).
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*/
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ldr r14, =EXC_RETURN /* Load the special value */
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msr primask, r3 /* Restore interrupts */
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/* Always return with R14 containing the special value that will: (1)
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* return to thread mode, and (2) continue to use the MSP
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*/
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bx r14 /* And return */
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.size handlers, .-handlers
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/************************************************************************************************
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* Name: up_interruptstack/g_intstackbase
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*
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* Description:
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* Shouldn't happen
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*
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************************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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.bss
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.global g_intstackbase
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.align 4
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up_interruptstack:
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.skip (CONFIG_ARCH_INTERRUPTSTACK & ~3)
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g_intstackbase:
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.size up_interruptstack, .-up_interruptstack
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#endif
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/************************************************************************************************
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* .rodata
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************************************************************************************************/
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.section .rodata, "a"
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/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
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* of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS
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* and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that
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* the system boots on and, eventually, becomes the idle, do nothing task that runs
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* only when there is nothing else to run. The heap continues from there until the
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* end of memory. See g_heapbase below.
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*/
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.globl g_heapbase
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.type g_heapbase, object
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g_heapbase:
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.word HEAP_BASE
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.size g_heapbase, .-g_heapbase
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.end
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