82 lines
4.0 KiB
C
82 lines
4.0 KiB
C
/****************************************************************************
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* arch/arm/include/armv8-m/nvicpri.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_ARM8_M_NVICPRI_H
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#define __ARCH_ARM_INCLUDE_ARM8_M_NVICPRI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <arch/chip/chip.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* If CONFIG_ARMV8M_USEBASEPRI is selected, then interrupts will be disabled
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* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
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* interrupts will not have execution priority. SVCall must have execution
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* priority in all cases.
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*
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* In the normal cases, interrupts are not nest-able and all interrupts run
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* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
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* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
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*
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* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
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* high priority interrupts are supported. These are not "nested" in the
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* normal sense of the word. These high priority interrupts can interrupt
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* normal processing but execute outside of OS (although they can "get back
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* into the game" via a PendSV interrupt).
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*
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* In the normal course of things, interrupts must occasionally be disabled
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* using the up_irq_save() inline function to prevent contention in use of
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* resources that may be shared between interrupt level and non-interrupt
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* level logic. Now the question arises, if we are using
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* CONFIG_ARCH_HIPRI_INTERRUPT=y, do we disable all interrupts except
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* SVCall (we cannot disable SVCall interrupts). Or do we only disable the
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* "normal" interrupts?
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*
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* If we are using the BASEPRI register to disable interrupts, then the
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* answer is that we must disable ONLY the "normal interrupts". That
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* is because we cannot disable SVCALL interrupts and we cannot permit
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* SVCAll interrupts running at a higher priority than the high priority
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* interrupts (otherwise, they will introduce jitter in the high priority
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* interrupt response time.)
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*
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* Hence, if you need to disable the high priority interrupt, you will have
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* to disable the interrupt either at the peripheral that generates the
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* interrupt or at the NVIC. Disabling global interrupts via the BASEPRI
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* register cannot effect high priority interrupts.
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*/
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/* The high priority interrupt must be highest priority. This prevents
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* SVCALL handling from adding jitter to high priority interrupt response.
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* Disabling interrupts will disable all interrupts EXCEPT SVCALL and the
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* high priority interrupts.
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*/
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#define NVIC_SYSH_MAXNORMAL_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT
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#define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_DEFAULT - 2*NVIC_SYSH_PRIORITY_STEP)
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#define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT
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#define NVIC_SYSH_SVCALL_PRIORITY (NVIC_SYSH_PRIORITY_DEFAULT - 1*NVIC_SYSH_PRIORITY_STEP)
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#endif /* __ARCH_ARM_INCLUDE_ARM8_M_NVICPRI_H */
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