464 lines
14 KiB
C
464 lines
14 KiB
C
/****************************************************************************
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* arch/arm/src/samd5e5/sam_wdt.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/timers/watchdog.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "sam_periphclks.h"
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#include "sam_wdt.h"
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#if defined(CONFIG_WATCHDOG) && defined(CONFIG_SAMD5E5_WDT)
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#ifndef BOARD_SCLK_FREQUENCY
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# define BOARD_SCLK_FREQUENCY 32768
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#endif
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#define WDT_FCLK (BOARD_SCLK_FREQUENCY / 128)
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#define WDT_MAXTIMEOUT ((1000 * (WDT_MR_WDV_MAX+1)) / WDT_FCLK)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/** N clock cycles */
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#define WDT_CLK_8CYCLE 8
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#define WDT_CLK_16CYCLE 16
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#define WDT_CLK_32CYCLE 32
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#define WDT_CLK_64CYCLE 64
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#define WDT_CLK_128CYCLE 128
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#define WDT_CLK_256CYCLE 256
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#define WDT_CLK_512CYCLE 512
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#define WDT_CLK_1024CYCLE 1024
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#define WDT_CLK_2048CYCLE 2048
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#define WDT_CLK_4096CYCLE 4096
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#define WDT_CLK_8192CYCLE 8192
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#define WDT_CLK_16384CYCLE 16384
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/**
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* \brief Macro is used to indicate the rate of second/millisecond
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*/
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#define WDT_PERIOD_RATE 1000
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/**
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* This structure provides the private representation of the "lower-half"
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* driver state structure. This structure must be cast-compatible with the
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* well-known watchdog_lowerhalf_s structure.
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*/
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struct sam_lowerhalf_s
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{
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const struct watchdog_ops_s *ops; /* Lower half operations */
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uint32_t timeout; /* The (actual) selected timeout */
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uint32_t lastreset; /* The last reset time */
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bool started; /* true: The watchdog timer has been started */
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uint8_t prescaler; /* Clock prescaler value */
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uint16_t reload; /* Timer reload value */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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void sam_sync_wdt(int value);
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/* "Lower half" driver methods **********************************************/
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static int sam_start(struct watchdog_lowerhalf_s *lower);
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static int sam_stop(struct watchdog_lowerhalf_s *lower);
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static int sam_keepalive(struct watchdog_lowerhalf_s *lower);
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static int sam_getstatus(struct watchdog_lowerhalf_s *lower,
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struct watchdog_status_s *status);
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static int sam_settimeout(struct watchdog_lowerhalf_s *lower,
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uint32_t timeout);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* "Lower half" driver methods */
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static const struct watchdog_ops_s g_wdgops =
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{
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.start = sam_start,
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.stop = sam_stop,
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.keepalive = sam_keepalive,
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.getstatus = sam_getstatus,
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.settimeout = sam_settimeout,
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.capture = NULL,
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.ioctl = NULL,
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};
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/* "Lower half" driver state */
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static struct sam_lowerhalf_s g_wdgdev;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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void sam_sync_wdt(int value)
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{
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while ((getreg32(SAM_WDT_SYNCBUSY) & value) != 0);
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}
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void sam_wdt_dumpregs(void)
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{
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wdinfo("WDT Regs:\n");
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wdinfo(" INTENCLR: %02x\n", getreg8(SAM_WDT_INTENCLR));
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wdinfo(" INTENSET: %02x\n", getreg8(SAM_WDT_INTENSET));
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wdinfo(" INTFLAG: %02x\n", getreg8(SAM_WDT_INTFLAG));
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wdinfo(" CTRLA: %02x\n", getreg8(SAM_WDT_CTRLA));
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wdinfo(" CONFIG: %02x\n", getreg8(SAM_WDT_CONFIG));
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wdinfo(" EWC: %02x\n", getreg8(SAM_WDT_EWCTRL));
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wdinfo(" CLEAR: %02x\n", getreg8(SAM_WDT_CLEAR));
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}
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/****************************************************************************
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* Name: sam_start
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*
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* Description:
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* Start the watchdog timer, resetting the time to the current timeout,
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation
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* of the "lower-half" driver state structure.
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int sam_start(struct watchdog_lowerhalf_s *lower)
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{
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struct sam_lowerhalf_s *priv = (struct sam_lowerhalf_s *)lower;
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irqstate_t flags;
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wdinfo("Entry: started=%d\n");
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DEBUGASSERT(priv);
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/* Have we already been started? */
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if (!priv->started)
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{
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/* Set up prescaler and reload value for the selected timeout before
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* starting the watchdog timer.
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*/
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/* Enable IWDG (the LSI oscillator will be enabled by hardware).
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* If the "Hardware watchdog" feature is enabled
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* through the device option bits,
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* the watchdog is automatically enabled at power-on.
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*/
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flags = enter_critical_section();
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putreg8(WDT_CTRLA_ENABLE, SAM_WDT_CTRLA);
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sam_sync_wdt(WDT_SYNCBUSY_ENABLE);
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priv->lastreset = clock_systime_ticks();
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priv->started = true;
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leave_critical_section(flags);
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}
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return OK;
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}
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/****************************************************************************
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* Name: sam_stop
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*
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* Description:
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* Stop the watchdog timer
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of
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* the "lower-half" driver state structure.
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int sam_stop(struct watchdog_lowerhalf_s *lower)
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{
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/* The watchdog is always disabled after a reset. It is enabled by clearing
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* the WDDIS bit in the WDT_CR register, then it cannot be disabled again
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* except by a reset.
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*/
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wdinfo("Entry\n");
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return -ENOSYS;
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}
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/****************************************************************************
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* Name: sam_keepalive
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*
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* Description:
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* Reset the watchdog timer to the current timeout value, prevent any
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* imminent watchdog timeouts. This is sometimes referred as "pinging"
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* the watchdog timer or "petting the dog".
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*
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* The application program must write in the SAM_WDT_CLEAR register
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* at regular intervals during normal operation to prevent an MCU reset.
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation
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* of the "lower-half" driver state structure.
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int sam_keepalive(struct watchdog_lowerhalf_s *lower)
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{
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struct sam_lowerhalf_s *priv = (struct sam_lowerhalf_s *)lower;
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irqstate_t flags;
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/* Reload the WDT timer */
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flags = enter_critical_section();
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putreg32(WDT_CLEAR_CLEAR, SAM_WDT_CLEAR);
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priv->lastreset = clock_systime_ticks();
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leave_critical_section(flags);
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return OK;
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}
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/****************************************************************************
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* Name: sam_getstatus
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*
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* Description:
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* Get the current watchdog timer status
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of
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* the "lower-half" driver state structure.
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* status - The location to return the watchdog status information.
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int sam_getstatus(struct watchdog_lowerhalf_s *lower,
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struct watchdog_status_s *status)
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{
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struct sam_lowerhalf_s *priv = (struct sam_lowerhalf_s *)lower;
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uint32_t ticks;
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uint32_t elapsed;
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wdinfo("Entry\n");
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DEBUGASSERT(priv);
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/* Return the status bit */
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status->flags = WDFLAGS_RESET;
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if (priv->started)
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{
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status->flags |= WDFLAGS_ACTIVE;
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}
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/* Return the actual timeout in milliseconds */
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status->timeout = priv->timeout;
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/* Get the elapsed time since the last ping */
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ticks = clock_systime_ticks() - priv->lastreset;
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elapsed = (int32_t)TICK2MSEC(ticks);
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if (elapsed > priv->timeout)
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{
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elapsed = priv->timeout;
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}
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/* Return the approximate time until the watchdog timer expiration */
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status->timeleft = priv->timeout - elapsed;
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wdinfo("Status :\n");
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wdinfo(" flags : %08x\n", status->flags);
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wdinfo(" timeout : %d\n", status->timeout);
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wdinfo(" timeleft : %d\n", status->timeleft);
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return OK;
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}
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/****************************************************************************
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* Name: sam_settimeout
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*
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* Description:
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* Set a new timeout value (and reset the watchdog timer)
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of
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* the "lower-half" driver state structure.
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* timeout - The new timeout value in millisecnds.
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static int sam_settimeout(struct watchdog_lowerhalf_s *lower,
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uint32_t timeout)
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{
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struct sam_lowerhalf_s *priv = (struct sam_lowerhalf_s *)lower;
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uint64_t tmp;
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uint32_t period_cycles;
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uint8_t timeout_period = WDT_CONFIG_PER_16K;
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irqstate_t flags;
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DEBUGASSERT(priv);
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wdinfo("Entry: timeout=%d\n", timeout);
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/* Can this timeout be represented? */
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flags = enter_critical_section();
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/* calc the period cycles corresponding to timeout period */
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tmp = (uint64_t)timeout * WDT_PERIOD_RATE;
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/* check whether overflow */
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if (tmp >> 32)
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{
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leave_critical_section(flags);
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return -ERANGE;
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}
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period_cycles = (uint32_t)tmp;
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/* calc the register value corresponding to period cysles */
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switch (period_cycles)
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{
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case WDT_CLK_8CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_8;
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break;
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case WDT_CLK_16CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_16;
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break;
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case WDT_CLK_32CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_32;
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break;
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case WDT_CLK_64CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_64;
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break;
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case WDT_CLK_128CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_128;
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break;
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case WDT_CLK_256CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_256;
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break;
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case WDT_CLK_512CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_512;
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break;
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case WDT_CLK_1024CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_1K;
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break;
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case WDT_CLK_2048CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_2K;
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break;
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case WDT_CLK_4096CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_4K;
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break;
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case WDT_CLK_8192CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_8K;
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break;
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case WDT_CLK_16384CYCLE *WDT_PERIOD_RATE:
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timeout_period = WDT_CONFIG_PER_16K;
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break;
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}
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if (!priv->started)
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putreg8(WDT_CONFIG_PER_16K, SAM_WDT_CONFIG);
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else
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putreg8(timeout_period, SAM_WDT_CONFIG);
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priv->reload = timeout_period;
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wdinfo("fwdt=%d reload=%d timeout=%d\n",
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WDT_FCLK, timeout_period, priv->timeout);
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leave_critical_section(flags);
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: sam_wdt_initialize
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*
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* Description:
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* Initialize the WDT watchdog timer. The watchdog timer
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* is initialized and registers as 'devpath'.
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*
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* Input Parameters:
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* devpath - The full path to the watchdog. This should be of the form
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* /dev/watchdog0
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void sam_wdt_initialize(const char *devpath)
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{
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struct sam_lowerhalf_s *priv = &g_wdgdev;
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DEBUGASSERT((getreg8(SAM_WDT_CTRLA) & WDT_CTRLA_ENABLE) == 0);
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sam_apb_wdt_enableperiph();
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/* Initialize the driver state structure. */
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priv->ops = &g_wdgops;
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priv->started = false;
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sam_settimeout((struct watchdog_lowerhalf_s *)priv,
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BOARD_SCLK_FREQUENCY / 2);
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watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv);
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}
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#endif /* CONFIG_WATCHDOG && CONFIG__WDT */
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