121 lines
3.6 KiB
C
121 lines
3.6 KiB
C
/****************************************************************************
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* arch/arm/src/stm32wb/stm32wb_ipcc.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "arm_internal.h"
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#include "chip.h"
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#include "stm32wb_ipcc.h"
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#include "hardware/stm32wb_rcc.h"
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#include "hardware/stm32wb_exti.h"
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#include "hardware/stm32wb_pwr.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32wb_ipccreset
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*
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* Description:
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* Reset the IPCC registers to default state
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*
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****************************************************************************/
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void stm32wb_ipccreset(void)
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{
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uint32_t regval;
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/* Disable CPU1 IPCC interrupts */
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putreg32(0x00000000, STM32WB_IPCC_C1CR);
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/* Clear CPU1 IPCC receive channel status */
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putreg32(IPCC_C1SCR_CLR_MASK, STM32WB_IPCC_C1SCR);
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/* Clear CPU2 IPCC receive channel status */
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putreg32(IPCC_C2SCR_CLR_MASK, STM32WB_IPCC_C2SCR);
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/* Disable CPU1 transmit/receive channels */
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regval = getreg32(STM32WB_IPCC_C1MR);
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regval |= IPCC_C1MR_OM_MASK | IPCC_C1MR_FM_MASK;
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putreg32(regval, STM32WB_IPCC_C1MR);
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/* Disable CPU2 transmit/receive channels */
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regval = getreg32(STM32WB_IPCC_C2MR);
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regval |= IPCC_C2MR_OM_MASK | IPCC_C2MR_FM_MASK;
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putreg32(regval, STM32WB_IPCC_C2MR);
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}
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/****************************************************************************
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* Name: stm32wb_ipccenable
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*
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* Description:
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* Enable the IPCC and start CPU2
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*
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****************************************************************************/
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void stm32wb_ipccenable(void)
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{
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uint32_t regval;
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/* CPU2 IPCC clock enable */
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regval = getreg32(STM32WB_RCC_C2AHB3ENR);
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regval |= RCC_C2AHB3ENR_IPCCEN;
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putreg32(regval, STM32WB_RCC_C2AHB3ENR);
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/* Enable EXTI event request for C1SEV interrupt to CPU2 */
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regval = getreg32(STM32WB_EXTI_C2EMR2);
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regval |= EXTI_C2EMR2_EM(EXTI_EVT_C1SEV);
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putreg32(regval, STM32WB_EXTI_C2EMR2);
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/* Enable EXTI rising edge trigger for C1SEV interrupt to CPU2 */
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regval = getreg32(STM32WB_EXTI_RTSR2);
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regval |= EXTI_RTSR2_RT(EXTI_EVT_C1SEV);
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putreg32(regval, STM32WB_EXTI_RTSR2);
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/* Set the internal event flag and send an event to CPU2 */
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__asm__ volatile ("sev");
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/* Clear the internal event flag */
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__asm__ volatile ("wfe");
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/* Boot CPU2 after reset or wakeup from stop or standby modes */
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regval = getreg32(STM32WB_PWR_CR4);
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regval |= PWR_CR4_C2BOOT;
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putreg32(regval, STM32WB_PWR_CR4);
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}
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