91 lines
4.1 KiB
C
91 lines
4.1 KiB
C
/****************************************************************************
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* arch/hc/src/m9s12/m9s12_int.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_HC_SRC_M9S12_M9S12_INT_H
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#define __ARCH_HC_SRC_M9S12_M9S12_INT_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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/* Offsets relative to CORE1 */
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#define HCS12_INT_ITCR_OFFSET 0x0015 /* Interrupt Test Control Register */
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#define HCS12_INT_ITEST_OFFSET 0x0016 /* Interrupt Test Registers */
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/* Offsets relative to CORE2 */
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#define HCS12_INT_HPRIO_OFFSET 0x0003 /* Highest Priority Interrupt */
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/* Register Addresses *******************************************************/
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#define HCS12_INT_ITCR (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_INT_ITCR_OFFSET)
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#define HCS12_INT_ITEST (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_INT_ITEST_OFFSET)
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#define HCS12_INT_HPRIO (HCS12_REG_BASE+HCS12_CORE2_BASE+HCS12_INT_HPRIO_OFFSET)
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/* Register Bit-Field Definitions *******************************************/
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/* Interrupt Test Control Register Bit-Field Definitions */
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#define INT_ITCR_ADR_SHIFT (0) /* Bits 0-3: Test register select */
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#define INT_ITCR_ADR_MASK (15 << INT_ITCR_ADR_SHIFT)
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#define INT_ITCR_WRTINT (1 << 4) /* Bit 4: Write to the Interrupt Test Registers */
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/* Interrupt Test Registers Bit-Field Definitions */
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#define INT_ITEST_INT(n) (1 << ((n) >> 1))
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#define INT_ITEST_INT0 (1 << 0) /* Bit 0: Test vector 0xffx0 */
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#define INT_ITEST_INT2 (1 << 1) /* Bit 1: Test vector 0xffx2 */
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#define INT_ITEST_INT4 (1 << 2) /* Bit 2: Test vector 0xffx4 */
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#define INT_ITEST_INT6 (1 << 3) /* Bit 3: Test vector 0xffx6 */
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#define INT_ITEST_INT8 (1 << 4) /* Bit 4: Test vector 0xffx8 */
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#define INT_ITEST_INTA (1 << 5) /* Bit 5: Test vector 0xffxa */
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#define INT_ITEST_INTC (1 << 6) /* Bit 6: Test vector 0xffxc */
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#define INT_ITEST_INTE (1 << 7) /* Bit 7: Test vector 0xffxe */
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/* Highest Priority Interrupt Bit-Field Definitions */
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/* Holds the least of the highest priority interrupt vector address */
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#define INT_HPRIO_MASK (0xfe)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_HC_SRC_M9S12_M9S12_INT_H */
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