83 lines
3.9 KiB
C
83 lines
3.9 KiB
C
/****************************************************************************
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* arch/hc/src/m9s12/m9s12_phy.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_HC_SRC_M9S12_M9S12_PHY_H
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#define __ARCH_HC_SRC_M9S12_M9S12_PHY_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define HCS12_PHY_EPHYCTL0_OFFSET 0x0000 /* Ethernet Physical Transceiver Control Register 0 */
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#define HCS12_PHY_EPHYCTL1_OFFSET 0x0001 /* Ethernet Physical Transceiver Control Register 1 */
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#define HCS12_PHY_EPHYSR_OFFSET 0x0002 /* Ethernet Physical Transceiver Status Register */
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/* Register Addresses *******************************************************/
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#define HCS12_PHY_EPHYCTL0 (HCS12_EPHY_BASE+HCS12_PHY_EPHYCTL0_OFFSET)
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#define HCS12_PHY_EPHYCTL1 (HCS12_EPHY_BASE+HCS12_PHY_EPHYCTL1_OFFSET)
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#define HCS12_PHY_EPHYSR (HCS12_EPHY_BASE+HCS12_PHY_EPHYSR_OFFSET)
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/* Register Bit-Field Definitions *******************************************/
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/* Ethernet Physical Transceiver Control Register 0 */
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#define PHY_EPHYCTL0_EPHYIEN (1 << 0) /* Bit 0: EPHY Interrupt Enable */
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#define PHY_EPHYCTL0_EPHYWAI (1 << 2) /* Bit 2: EPHY Module Stops While in Wait */
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#define PHY_EPHYCTL0_LEDEN (1 << 3) /* Bit 3: LED Drive Enable */
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#define PHY_EPHYCTL0_DIS10 (1 << 4) /* Bit 4: Disable 10BASE-T PLL */
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#define PHY_EPHYCTL0_DIS100 (1 << 5) /* Bit 5: Disable 100 BASE-TX PLL */
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#define PHY_EPHYCTL0_ANDIS (1 << 6) /* Bit 6: Auto Negotiation Disable */
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#define PHY_EPHYCTL0_EPHYEN (1 << 7) /* Bit 7: EPHY Enable */
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/* Ethernet Physical Transceiver Control Register 1 */
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#define PHY_EPHYCTL1_PHYADD_SHIFT (0) /* Bits 0-4: EPHY Address for MII Requests */
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#define PHY_EPHYCTL1_PHYADD_MASK (0x1f)
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/* Ethernet Physical Transceiver Status Register */
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#define PHY_EPHYSR_EPHYI (1 << 0) /* Bit 0: EPHY Interrupt Flag */
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#define PHY_EPHYSR_10DIS (1 << 4) /* Bit 4: EPHY Port 10BASE-T mode status */
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#define PHY_EPHYSR_100DIS (1 << 5) /* Bit 5: EPHY Port 100BASE-TX mode status */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_HC_SRC_M9S12_M9S12_PHY_H */
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