nuttx/arch/xtensa/include/esp32
Tiago Medicci Serrano 57b8fc9954 esp32/irq: Allow IRAM ISRs to run during SPI flash operation
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.

It also makes the code look more similar to the ESP32-S3 SPI flash
implementation by creating a common `esp32_spiflash_init` that is
responsible to create the SPI flash operation tasks. The function
intended to initialize the SPI flash partions was, then, renamed to
`board_spiflash_init`.
2023-11-10 09:11:35 +08:00
..
chip.h
core-isa.h libc/machine/xtensa: make longjmp safe against context switch 2022-11-22 19:34:44 +01:00
esp32_himem_chardev.h arch: xtensa/esp32: Add esp32_himem_chardev.c 2023-01-14 14:07:46 +08:00
esp_efuse_table.h
irq.h esp32/irq: Allow IRAM ISRs to run during SPI flash operation 2023-11-10 09:11:35 +08:00
memory_layout.h Fix nuttx coding style 2023-07-14 01:16:06 +08:00
tie-asm.h
tie.h include: fix double include pre-processor guards 2022-01-16 11:11:14 -03:00