246 lines
9.4 KiB
Plaintext
246 lines
9.4 KiB
Plaintext
README
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======
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This README discusses issues unique to NuttX configurations for the
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IQ-Analog NR5M100 FPGA implementation of a RISC-V core on the Digilent
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Nexys4 FPGA board.
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The port is currently very minimal, though additional support may be
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added in the future to address more of the board peripherals supplied
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on the FPGA board. Those peripherals include:
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Supported:
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- USB UART (console port)
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- 16 single color LEDs
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- 16 slide switch inputs
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- Two tri-color LEDs
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- 5 Joystick style pushbuttons
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- 16 GPIO pins on 2 of the PMOD expansion connectors
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Not supported:
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- VGA display port
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- 8 digit 7-segement display
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- SD card slot
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- SPI FLASH memory (shared with FPGA configuration data).
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- USB HID (single device) connector serviced by external PIC uC
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- Non-DDR (older version): 16 MB Cellular SRAM
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- DDR (newer version): 128 MB DDR2 SDRAM
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- Microphone
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- 10/100 Ethernet PHY
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- 3-Axis accelerometer
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- Temperature sensor
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See http://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/
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or http://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/
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for more information about these boards.
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Contents
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========
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- NR5M100 Overview
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- Development Environment
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- GNU Toolchain Options
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- Debugger
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- IDEs
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- LEDs
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- PWM
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- UARTs
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- Timer Inputs/Outputs
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- FSMC SRAM
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- SSD1289
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- Mikroe-STM32F4-specific Configuration Options
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- Configurations
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Development Environment
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=======================
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The NR5M100 RISC-V core was designed as a low gate count / low performance micro controller
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for inclusion in an ASIC. It is based on a Verilog RISC-V called picorv32, but has many
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additions beyond that baseline. The design running on the Digilent Nexys4 FPGA is a
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validation platform for the core and is presented as an open source project.
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The reason NR5M100 is "low performance" is that it is a state machine based core (like the
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picorv32) and not a multi-stage pipeline core. This means that it requires an average of
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4.5 clock cycles to execute each instruction. On a multi-stage pipeline architecure, this
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average would be closer to 1 clock cycle per instruction (though a bit higher due to
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pipeline branch misses). The tradeoff for lower performance is a simpler design. There
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is a single memory bus interface for both instructions and data. Multi-stage pipeline
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cores require a separate I and D bus with cache SRAM and an external memory cache controller,
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etc. This in addition to the pipeline registers adds additional gate count.
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The nr5m100-nexys4 core runs at 83.333 Mhz which provides about 18 Mhz effective operating
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speed with the multi-clock per instruction architecture. If you are looking for a higher
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performance platform, you should check out the PULP Platform ( http://www.pulp-platform.org ).
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That is an FPGA design with a 4-stage pipeline RISC-V core, though not currently supported
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by NuttX. The NR5M100 project will likely pull in the RISC-V core from that design next,
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though this will probably not be available soon. With a bit of work, it is possible to
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run the nr5m100-nexys4 core at 170 Mhz with a 6.5 clocks-per-instruction state machine.
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This would give an effective performance of about 26Mhz.
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Development Environment
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=======================
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Linux is the best choice for development, though Cygwin on Windows may work.
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The source has been built only using the GNU toolchain (see below) under a Linux
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environment. Other toolchains will likely cause problems or not be available yet.
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RISC-V GNU Toolchain
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====================
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To compile the code, you must first build a RISC-V GNU Toolchain from the sources at
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https://github.com/riscv/riscv-gnu-toolchain. I don't know of any sources for pre-compiled
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toolchains (though there may be some out there).
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To build this toolchain, follow these instructions (tested on Ubuntu 12.04):
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1. Create a working directory in your home folder:
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mkdir ~/riscv
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cd ~/riscv
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2. Clone the GNU source tree:
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git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
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3. Ensure the following packages are installed:
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sudo apt-get install texinfo bison flex autoconf automake libgmp-dev libmpfr-dev libmpc-dev
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4. Configure and build the toolchain:
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cd riscv-gnu-toolchain
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./configure --with-xlen=64 --with-arch=I --disable-float --disable-atomic --enable-multilib --prefix=~/riscv
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make -j4 (or -j8 based on how many cores you have)
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5. Setup your PATH environment variable to include the toolchain (you may want to add this to
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your shell login script, such as .bash_profile, etc.):
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export PATH=~/riscv/bin:$PATH
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Windows based toolchain
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-----------------------
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May be possible to compile the GNU toolchain described above using Cygwin, but havne't tried it.
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Debugger
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========
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The Debug Module within the NR5M100 RISC-V has been designed to work with the RISC-V gdb
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debugger interfaced with the SiFive implementation of OpenOCD. The interface has been tested
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with a J-LINK JTAG probe connected to PMOD header B on the FPGA using an adapter board
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that I designed and fabbed at OSHPark. I will update this README.txt file soon with a link
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to the shared project for anyone who wishes to build one.
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To build OpenOCD, perform the following:
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1. Ensure the proper packages are installed:
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sudo apt-get install autoconf automake libtool libusb-1.0-0-dev
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2. Download the latest OpenOCD sources from the SiFive github repo:
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cd ~/riscv
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git clone --recursive https://github.com/sifive/openocd.git
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3. Configure and build OpenOCD. The x86_64 GCC compilers will give errors because of
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shadowed variable warnings, so diable the -Werror flag also:
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cd openocd
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sed -i 's/ -Werror//g' configure.ac
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./bootstrap
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./configure --enable-jlink --enable-maintainer-mode --enable-ftdi --prefix=~/riscv CFLAGS=-g
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The configuration scripts for openocd and nr5m100-nexys4 have been provided in the
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nuttx/configs/nr5m100-nexys4/scripts directory. They are configured to use a J-LINK JTAG
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probe and to search for the IQ-Analog (the company I work for) IDCODE and part number for
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the FPGA board (7a10 for Artix xc7a100 part on the Digilent Nexys4 board). With FPGA
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source directly from the nr5m100 github site (to be provided), this ID will match the
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hardware. If changes are made to the JEDEC ID and/or part number, then the nr5m100.cfg
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file will need to be modified with the proper CPUID value.
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IDEs
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====
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NuttX is built using command-line make. It can be used with an IDE, but some
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effort will be required to create the project. While I haven't tried it as
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I am not an IDE guy, the team at SiFive have reported that they now have
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Eclipse working with the RISC-V gdb debugger.
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NOTE: The notes below are taken from an ARM build of NuttX, not RISC-V, so
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they may or may not work. Try it and see I suppose.
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Makefile Build
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--------------
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Under Eclipse, it is pretty easy to set up an "empty makefile project" and
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simply use the NuttX makefile to build the system. That is almost for free
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under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
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makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
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there is a lot of help on the internet).
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Native Build
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------------
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Here are a few tips before you start that effort:
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1) Select the toolchain that you will be using in your .config file
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2) Start the NuttX build at least one time from the Cygwin command line
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before trying to create your project. This is necessary to create
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certain auto-generated files and directories that will be needed.
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3) Set up include pathes: You will need include/, arch/risc-v/src/rv32im,
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arch/risc-v/src/common, arch/risc-v/src/nr5m100, and sched/.
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4) All assembly files need to have the definition option -D __ASSEMBLY__
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on the command line.
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Startup files will probably cause you some headaches. The NuttX startup file
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is arch/risc-v/src/nr5m100/nr5_vectors.S. With RIDE, I build NuttX
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one time from the Cygwin command line in order to obtain the pre-built
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startup object needed by RIDE.
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LEDs
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====
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The Nexys4 board has 16 single-color LEDs onboard, as well as 2 tri-color LEDs.
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These are supported using GPIO Ports A (16-single color) and B (tri-color).
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Additionally the tri-color LEDs can be driven from the Timer 1 or 2 PWM output
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signals.
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PWM
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===
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The nr5m100-nexys4 design has PWM capabilities within the Timer 1 and Timer 2
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modules. These PWM signals can be muxed to the tri-color LEDs or to I/O
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pins on one of the PMOD expansion headers.
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UARTs
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=====
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The nr5m100-nexys4 design has an onboard USB-UART providing an RS-232 interface
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via the same USB cable that is used to program the FPGA. The core proivdes a
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fixed 8-Data bit, 1 stop bit, no parity UART connected to this intrface.
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UART PINS
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---------
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UART1
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RX FPGA C4 (USB UART device)
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TX FPGA D4 (USB UART device)
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Default USART/UART Configuration
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--------------------------------
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UART1 is enabled in all configurations (see */defconfig).
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Configurations
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==============
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Each nr5m100-nexys4 configuration is maintained in a sub-directory and
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can be selected as follow:
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cd tools
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./configure.sh nr5m100-nexys4/<subdir>
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cd -
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Where <subdir> is one of the following:
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nsh
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---
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This is an NSH example that uses UART1 as the console. UART1 is connected
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to the USB UART bridge on the FPGA board.
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