319 lines
8.9 KiB
C
319 lines
8.9 KiB
C
/****************************************************************************
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* arch/mips/src/pic32mx/pic32mx_gpio.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <errno.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "mips_internal.h"
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#include "chip.h"
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#include "pic32mx_ioport.h"
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#include "pic32mx.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static const uintptr_t g_gpiobase[CHIP_NPORTS] =
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{
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PIC32MX_IOPORTA_K1BASE
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#if CHIP_NPORTS > 1
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, PIC32MX_IOPORTB_K1BASE
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#endif
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#if CHIP_NPORTS > 2
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, PIC32MX_IOPORTC_K1BASE
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#endif
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#if CHIP_NPORTS > 3
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, PIC32MX_IOPORTD_K1BASE
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#endif
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#if CHIP_NPORTS > 4
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, PIC32MX_IOPORTE_K1BASE
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#endif
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#if CHIP_NPORTS > 5
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, PIC32MX_IOPORTF_K1BASE
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#endif
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#if CHIP_NPORTS > 6
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, PIC32MX_IOPORTG_K1BASE
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: Inline PIN set field extractors
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****************************************************************************/
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static inline bool pic32mx_output(uint16_t pinset)
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{
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return ((pinset & GPIO_OUTPUT) != 0);
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}
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static inline bool pic32mx_opendrain(uint16_t pinset)
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{
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return ((pinset & GPIO_MODE_MASK) == GPIO_OPENDRAN);
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}
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static inline bool pic32mx_outputhigh(uint16_t pinset)
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{
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return ((pinset & GPIO_VALUE_MASK) != 0);
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}
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static inline unsigned int pic32mx_portno(uint16_t pinset)
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{
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return ((pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
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}
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static inline unsigned int pic32mx_pinno(uint16_t pinset)
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{
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return ((pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
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}
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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static inline unsigned int pic32mx_analog(uint16_t pinset)
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{
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return ((pinset & GPIO_ANALOG_MASK) != 0);
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}
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#else
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# define pic32mx_analog(pinset) (false)
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: pic32mx_configgpio
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*
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin (the
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* interrupt will be configured when pic32mx_attach() is called.
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*
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* Returned Value:
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* OK on success; negated errno on failure.
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*
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****************************************************************************/
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int pic32mx_configgpio(uint16_t cfgset)
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{
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unsigned int port = pic32mx_portno(cfgset);
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unsigned int pin = pic32mx_pinno(cfgset);
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uint32_t mask = (1 << pin);
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uintptr_t base;
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/* Verify that the port number is within range */
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if (port < CHIP_NPORTS)
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{
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/* Get the base address of the ports */
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base = g_gpiobase[port];
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/* Is this an input or an output? */
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sched_lock();
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if (pic32mx_output(cfgset))
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{
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/* Not analog */
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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putreg32(mask, base + PIC32MX_IOPORT_ANSELCLR_OFFSET);
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#endif
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/* It is an output; clear the corresponding bit in TRIS register */
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putreg32(mask, base + PIC32MX_IOPORT_TRISCLR_OFFSET);
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/* Is it an open drain output? */
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if (pic32mx_opendrain(cfgset))
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{
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/* It is an open drain output. Set the corresponding bit in
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* the ODC register.
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*/
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putreg32(mask, base + PIC32MX_IOPORT_ODCSET_OFFSET);
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}
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else
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{
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/* Is is a normal output. Clear the corresponding bit in the
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* ODC register.
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*/
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putreg32(mask, base + PIC32MX_IOPORT_ODCCLR_OFFSET);
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}
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/* Set the initial output value */
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pic32mx_gpiowrite(cfgset, pic32mx_outputhigh(cfgset));
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}
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else
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{
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/* It is an input; set the corresponding bit in TRIS register. */
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putreg32(mask, base + PIC32MX_IOPORT_TRISSET_OFFSET);
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putreg32(mask, base + PIC32MX_IOPORT_ODCCLR_OFFSET);
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/* Is it an analog input? */
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#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
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if (pic32mx_analog(cfgset))
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{
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putreg32(mask, base + PIC32MX_IOPORT_ANSELSET_OFFSET);
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}
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else
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{
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putreg32(mask, base + PIC32MX_IOPORT_ANSELCLR_OFFSET);
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}
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#endif
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}
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sched_unlock();
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return OK;
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}
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return -EINVAL;
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}
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/****************************************************************************
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* Name: pic32mx_gpiowrite
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*
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* Description:
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* Write one or zero to the selected GPIO pin
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*
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****************************************************************************/
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void pic32mx_gpiowrite(uint16_t pinset, bool value)
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{
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unsigned int port = pic32mx_portno(pinset);
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unsigned int pin = pic32mx_pinno(pinset);
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uintptr_t base;
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/* Verify that the port number is within range */
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if (port < CHIP_NPORTS)
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{
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/* Get the base address of the ports */
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base = g_gpiobase[port];
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/* Set or clear the output */
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if (value)
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{
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putreg32(1 << pin, base + PIC32MX_IOPORT_PORTSET_OFFSET);
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}
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else
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{
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putreg32(1 << pin, base + PIC32MX_IOPORT_PORTCLR_OFFSET);
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}
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}
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}
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/****************************************************************************
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* Name: pic32mx_gpioread
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*
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* Description:
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* Read one or zero from the selected GPIO pin
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*
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****************************************************************************/
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bool pic32mx_gpioread(uint16_t pinset)
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{
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unsigned int port = pic32mx_portno(pinset);
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unsigned int pin = pic32mx_pinno(pinset);
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uintptr_t base;
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/* Verify that the port number is within range */
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if (port < CHIP_NPORTS)
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{
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/* Get the base address of the ports */
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base = g_gpiobase[port];
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/* Get and return the input value */
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return (getreg32(base + PIC32MX_IOPORT_PORT_OFFSET) & (1 << pin)) != 0;
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}
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return false;
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}
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/****************************************************************************
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* Function: pic32mx_dumpgpio
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*
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* Description:
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* Dump all GPIO registers associated with the provided base address
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_GPIO_INFO
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void pic32mx_dumpgpio(uint32_t pinset, const char *msg)
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{
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unsigned int port = pic32mx_portno(pinset);
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irqstate_t flags;
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uintptr_t base;
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/* Verify that the port number is within range */
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if (port < CHIP_NPORTS)
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{
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/* Get the base address of the ports */
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base = g_gpiobase[port];
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/* The following requires exclusive access to the GPIO registers */
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sched_lock();
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gpioinfo("IOPORT%c pinset: %04x base: %08x -- %s\n",
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'A' + port, pinset, base, msg);
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gpioinfo(" TRIS: %08x PORT: %08x LAT: %08x ODC: %08x\n",
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getreg32(base + PIC32MX_IOPORT_TRIS_OFFSET),
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getreg32(base + PIC32MX_IOPORT_PORT_OFFSET),
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getreg32(base + PIC32MX_IOPORT_LAT_OFFSET),
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getreg32(base + PIC32MX_IOPORT_ODC_OFFSET));
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gpioinfo(" CNCON: %08x CNEN: %08x CNPUE: %08x\n",
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getreg32(PIC32MX_IOPORT_CNCON),
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getreg32(PIC32MX_IOPORT_CNEN),
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getreg32(PIC32MX_IOPORT_CNPUE));
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sched_unlock();
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}
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}
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#endif
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