4ec7af779d
When I try to set priorities in certain programs, such as init_priority(HIGH_PRIORITY), I've noticed that during linking, there's no guarantee that the programs will be compiled in the sequence I've specified based on priority. This has led to some runtime errors in my program. I realized that in the ld file, when initializing dynamic arrays, there's no assurance of initializing init_array.* before init_array. This has resulted in runtime errors in the program. Consequently, I've rearranged the init_array.* in the ld file of NuttX to be placed before init_array and added a SORT operation to init_array.* to ensure accurate initialization based on priorities during linking.
118 lines
3.6 KiB
Plaintext
118 lines
3.6 KiB
Plaintext
/****************************************************************************
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* boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-sdram.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* The LPC1788 has 512Kb of FLASH beginning at address 0x0000:0000 and
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* 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address
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* 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses
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* 0x20000000 bank0 first and 8kb at 0x20002000 at bank0 second. And 16Kb
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* at 0x20004000 on bank1.
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*
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* Here we assume that .data and .bss will all fit into the 64Kb CPU SRAM
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* address range.
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*/
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MEMORY
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{
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FLASHBOOT (rx) : ORIGIN = 0x00000000, LENGTH = 0x00007000
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KEYVAL (rx) : ORIGIN = 0x00007000, LENGTH = 0x00002000
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FLASH (rx) : ORIGIN = 0x00009000, LENGTH = 0x00077000
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SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
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AHBRAM8_B0A(rwx): ORIGIN = 0x20000000, LENGTH = 8K
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AHBRAM8_B0B(rwx): ORIGIN = 0x20002000, LENGTH = 8K
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AHBRAM16(rwx): ORIGIN = 0x20004000, LENGTH = 16K
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/* External SDRAM - 32MB for LX_CPU */
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SDRAM (rwx) : ORIGIN = 0xA0000000, LENGTH = 32M
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}
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OUTPUT_ARCH(arm)
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EXTERN(_vectors)
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ENTRY(_stext)
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SECTIONS
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{
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.text : {
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_stext = ABSOLUTE(.);
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*(.vectors)
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > SDRAM
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.init_section : ALIGN(16) {
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_sinit = ABSOLUTE(.);
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KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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KEEP(*(.init_array .ctors))
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_einit = ABSOLUTE(.);
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} > SDRAM
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.ARM.extab : ALIGN(16) {
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*(.ARM.extab*)
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} > SDRAM
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.ARM.exidx : ALIGN(16) {
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__exidx_start = ABSOLUTE(.);
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*(.ARM.exidx*)
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__exidx_end = ABSOLUTE(.);
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} > SDRAM
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.data : ALIGN(16) {
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} > SRAM AT > SDRAM
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_eronly = LOADADDR(.data);
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.bss : {
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = ABSOLUTE(.);
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} > SRAM
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/* Stabs debugging sections */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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}
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