380 lines
12 KiB
C
380 lines
12 KiB
C
/****************************************************************************
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* boards/arm/stm32h7/openh743i/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/* Do not include STM32 H7 header files here */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The Openh743i board provides the following clock sources:
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*
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* X2: 32.768 KHz crystal for LSE
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* X2: 8 MHz HSE crystal oscillator
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 16 MHz RC factory-trimmed
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* LSI: 32 KHz RC
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* HSE: 8 MHz oscillator X2
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* LSE: 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE = 8,000,000
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*
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* When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected.
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* VCOH otherwise.
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*
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* PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 1 <= PLLM <= 63
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* 4 <= PLLN <= 512
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* 150 MHz <= PLL_VCOL <= 420MHz
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* 192 MHz <= PLL_VCOH <= 836MHz
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*
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* SYSCLK = PLL_VCO / PLLP
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* CPUCLK = SYSCLK / D1CPRE
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* Subject to
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*
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* PLLP1 = {2, 4, 6, 8, ..., 128}
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* PLLP2,3 = {2, 3, 4, ..., 128}
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* CPUCLK <= 400 MHz
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*/
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#define STM32_BOARD_USEHSE
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#undef STM32_HSEBYP_ENABLE
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#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE
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/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
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*
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* PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz
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*
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* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
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* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz
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* PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz
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*/
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#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVP1EN | \
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RCC_PLLCFGR_DIVQ1EN | \
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RCC_PLLCFGR_DIVR1EN)
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#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2)
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#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(200)
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#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2)
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#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4)
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#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8)
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#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200)
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#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
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#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
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#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8)
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/* PLL2 */
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#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVP2EN)
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#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2)
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#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(200)
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#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(40)
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#define STM32_PLLCFG_PLL2Q 0
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#define STM32_PLLCFG_PLL2R 0
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#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200)
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#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2)
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#define STM32_PLL2Q_FREQUENCY
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#define STM32_PLL2R_FREQUENCY
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/* PLL3, wide 1 - 2 MHz input, enable DIVQ
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*
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* PLL3_VCO = (8,000,000 / 8) * 336 = 336 MHz
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*
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* PLL3P - TODO
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* PLL3Q = PLL3_VCO / 7 = 336 MHz / 7 = 48 MHz
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* PLL3R - TODO
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*/
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#define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL3RGE_1_2_MHZ | \
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RCC_PLLCFGR_DIVQ3EN)
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#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(8)
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#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(336)
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#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2)
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#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(7)
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#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(2)
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#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 100)
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#define STM32_PLL3P_FREQUENCY
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#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 8)
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#define STM32_PLL3R_FREQUENCY
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/* SYSCLK = PLL1P = 400 MHz
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* CPUCLK = SYSCLK / 1 = 400 MHz
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*/
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#define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK)
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#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY)
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#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1)
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/* Configure Clock Assignments */
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/* AHB clock (HCLK) is SYSCLK/2 (200 MHz max)
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* HCLK1 = HCLK2 = HCLK3 = HCLK4
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*/
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#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */
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#define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */
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#define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */
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/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* APB2 clock (PCLK2) is HCLK/4 (54 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd4 /* PCLK2 = HCLK / 4 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* APB3 clock (PCLK3) is HCLK/4 (54 MHz) */
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#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd4 /* PCLK3 = HCLK / 4 */
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#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* APB4 clock (PCLK4) is HCLK/4 (54 MHz) */
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#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd4 /* PCLK4 = HCLK / 4 */
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#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timer clock frequencies */
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Kernel Clock Configuration
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*
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* Note: look at Table 54 in ST Manual
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*/
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/* I2C123 clock source - HSI */
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#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI
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/* I2C4 clock source - HSI */
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#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI
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/* SPI123 clock source - PLL1Q */
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#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1
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/* SPI45 clock source - APB (PCLK2?) */
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#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_APB
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/* SPI6 clock source - APB (PCLK4) */
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#define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PCLK4
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#if 1
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/* USB 1 and 2 clock source - HSI48 */
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# define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48
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#else
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/* USB 1 and 2 clock source - PLL3Q */
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# define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3
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#endif
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/* ADC 1 2 3 clock source - pll2_pclk */
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#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2
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/* FLASH wait states
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*
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* ------------ ---------- -----------
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* Vcore MAX ACLK WAIT STATES
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* ------------ ---------- -----------
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* 1.15-1.26 V 70 MHz 0
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* (VOS1 level) 140 MHz 1
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* 210 MHz 2
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* 1.05-1.15 V 55 MHz 0
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* (VOS2 level) 110 MHz 1
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* 165 MHz 2
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* 220 MHz 3
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* 0.95-1.05 V 45 MHz 0
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* (VOS3 level) 90 MHz 1
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* 135 MHz 2
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* 180 MHz 3
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* 225 MHz 4
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* ------------ ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 2
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#define BOARD_FLASH_PROGDELAY 3
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#define STM32_PWR_VOS_SCALE PWR_D3CR_VOS_SCALE_1
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#define STM32_VOS_OVERDRIVE 1 /* Enable VOS0 */
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/* SDMMC definitions ********************************************************/
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/* Init 400kHz, PLL1Q/(2*250) */
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#define STM32_SDMMC_INIT_CLKDIV (250 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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/* Set these to 20 MHz (PLL1Q/(2*5)).
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* Higher frequency doesn't work, probably due to poor board
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* signal integrity
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*/
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#define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
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/* LED definitions **********************************************************/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_LED4 3
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#define BOARD_NLEDS 4
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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#define BOARD_LED4_BIT (1 << BOARD_LED4)
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/* Alternate function pin selections ****************************************/
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/* USART1 (CP2102 converter) */
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#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PA10 */
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#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PA9 */
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/* USART3 */
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
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/* USB OTG ULPI */
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#define GPIO_OTG_HS_ULPI_CK (GPIO_OTG_HS_ULPI_CK_0|GPIO_SPEED_100MHz)
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#define GPIO_OTG_HS_ULPI_D0 (GPIO_OTG_HS_ULPI_D0_0|GPIO_SPEED_100MHz)
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#define GPIO_OTG_HS_ULPI_D1 (GPIO_OTG_HS_ULPI_D1_0|GPIO_SPEED_100MHz)
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#define GPIO_OTG_HS_ULPI_D2 (GPIO_OTG_HS_ULPI_D2_0|GPIO_SPEED_100MHz)
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#define GPIO_OTG_HS_ULPI_D3 (GPIO_OTG_HS_ULPI_D3_0|GPIO_SPEED_100MHz)
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#define GPIO_OTG_HS_ULPI_D4 (GPIO_OTG_HS_ULPI_D4_0|GPIO_SPEED_100MHz)
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#define GPIO_OTG_HS_ULPI_D5 (GPIO_OTG_HS_ULPI_D5_0|GPIO_SPEED_100MHz)
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#define GPIO_OTG_HS_ULPI_D6 (GPIO_OTG_HS_ULPI_D6_0|GPIO_SPEED_100MHz)
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#define GPIO_OTG_HS_ULPI_D7 (GPIO_OTG_HS_ULPI_D7_0|GPIO_SPEED_100MHz)
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#define GPIO_OTG_HS_ULPI_DIR (GPIO_OTG_HS_ULPI_DIR_1|GPIO_SPEED_100MHz) /* PC2 */
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#define GPIO_OTG_HS_ULPI_NXT (GPIO_OTG_HS_ULPI_NXT_1|GPIO_SPEED_100MHz) /* PC3 */
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#define GPIO_OTG_HS_ULPI_STP (GPIO_OTG_HS_ULPI_STP_0|GPIO_SPEED_100MHz)
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/* OTGFS */
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#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz)
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#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz)
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#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz)
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/* SDMMC */
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#define GPIO_SDMMC1_D0 (GPIO_SDMMC1_D0_0|GPIO_SPEED_50MHz)
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#define GPIO_SDMMC1_D1 (GPIO_SDMMC1_D1_0|GPIO_SPEED_50MHz)
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#define GPIO_SDMMC1_D2 (GPIO_SDMMC1_D2_0|GPIO_SPEED_50MHz)
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#define GPIO_SDMMC1_D3 (GPIO_SDMMC1_D3_0|GPIO_SPEED_50MHz)
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#define GPIO_SDMMC1_CK (GPIO_SDMMC1_CK_0|GPIO_SPEED_50MHz)
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#define GPIO_SDMMC1_CMD (GPIO_SDMMC1_CMD_0|GPIO_SPEED_50MHz)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H */
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