576 lines
22 KiB
C
576 lines
22 KiB
C
/****************************************************************************
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* boards/arm/samv7/samv71-xult/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAMV7_SAMV71_XULT_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAMV7_SAMV71_XULT_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* After power-on reset, the SAMV71Q device is running out of the Master
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* Clock using the Fast RC Oscillator running at 4 MHz.
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*
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* MAINOSC: Frequency = 12MHz (crystal)
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*
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* 300MHz Settings:
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* PLLA: PLL Divider = 1, Multiplier = 20 to generate PLLACK = 240MHz
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* Master Clock (MCK):
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* Source = PLLACK,
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* Prescalar = 1 to generate MCK = 120MHz
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* CPU clock: 120MHz
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*
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* There are two on-board crystals:
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*/
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#define BOARD_HAVE_SLOWXTAL 1 /* Slow crystal is populated */
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#define BOARD_SLOWCLK_FREQUENCY (32768) /* 32.768 KHz slow crystal oscillator */
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* 12 MHz main oscillator */
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/* Main oscillator register settings.
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*
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* The main oscillator could be either the embedded 4/8/12 MHz fast RC
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* oscillators or an external 3-20 MHz crystal or ceramic resonator.
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* The external clock source is selected by default in sam_clockconfig.c.
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* Here we need to specify the main oscillator start-up time.
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*
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* REVISIT... this is old information:
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* The start up time should be should be:
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*
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* Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
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*/
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#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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#define BOARD_CKGR_MOR_MOSCXTENBY (PMC_CKGR_MOR_MOSCXTEN) /* Crystal Oscillator Enable */
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/* PLLA configuration.
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*
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* Divider = 1
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* Multiplier = 25
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*
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* Yields:
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*
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* PLLACK = 25 * 12MHz / 1 = 300MHz
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*/
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#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_MUL PMC_CKGR_PLLAR_MUL(24)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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/* PMC master clock register settings.
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*
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* BOARD_PMC_MCKR_CSS - The source of main clock input. This may be one of:
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*
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* PMC_MCKR_CSS_SLOW Slow Clock
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* PMC_MCKR_CSS_MAIN Main Clock
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* PMC_MCKR_CSS_PLLA PLLA Clock
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* PMC_MCKR_CSS_UPLL Divided UPLL Clock
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*
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* BOARD_PMC_MCKR_PRES - Source clock pre-scaler. May be one of:
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*
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* PMC_MCKR_PRES_DIV1 Selected clock
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* PMC_MCKR_PRES_DIV2 Selected clock divided by 2
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* PMC_MCKR_PRES_DIV4 Selected clock divided by 4
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* PMC_MCKR_PRES_DIV8 Selected clock divided by 8
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* PMC_MCKR_PRES_DIV16 Selected clock divided by 16
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* PMC_MCKR_PRES_DIV32 Selected clock divided by 32
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* PMC_MCKR_PRES_DIV64 Selected clock divided by 64
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* PMC_MCKR_PRES_DIV3 Selected clock divided by 3
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*
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* The prescaler determines (1) the CPU clock and (2) the input into the
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* second divider that then generates the Master Clock (MCK). MCK is the
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* source clock of the peripheral clocks.
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*
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* BOARD_PMC_MCKR_MDIV - MCK divider. May be one of:
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*
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* PMC_MCKR_MDIV_DIV1 Master Clock = Prescaler Output Clock / 1
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* PMC_MCKR_MDIV_DIV2 Master Clock = Prescaler Output Clock / 2
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* PMC_MCKR_MDIV_DIV4 Master Clock = Prescaler Output Clock / 4
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* PMC_MCKR_MDIV_DIV3 Master Clock = Prescaler Output Clock / 3
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*/
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA /* Source = PLLA */
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 /* Prescaler = /1 */
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#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_DIV2 /* MCK divider = /2 */
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/* USB clocking */
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#define BOARD_PMC_MCKR_UPLLDIV2 0 /* UPLL clock not divided by 2 */
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/* Resulting frequencies */
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#define BOARD_PLLA_FREQUENCY (300000000) /* PLLACK: 25 * 12Mhz / 1 */
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#define BOARD_CPU_FREQUENCY (300000000) /* CPU: PLLACK / 1 */
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#define BOARD_MCK_FREQUENCY (150000000) /* MCK: PLLACK / 1 / 2 */
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#undef BOARD_UPLL_FREQUENCY /* To be provided */
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV) + CLOCKODD + 2).
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*
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* MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2)
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*
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* Where CLKDIV has a range of 0-255.
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*/
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/* MCK = 150MHz,
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* CLKDIV = 186,
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* MCI_SPEED = 150MHz / (2*186 + 1 + 2) = 400 KHz
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*/
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#define HSMCI_INIT_CLKDIV ((186 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)
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/* MCK = 150MHz,
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* CLKDIV = 3 w/CLOCKODD,
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* MCI_SPEED = 150MHz /(2*3 + 0 + 2) = 18.75 MHz
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*/
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#define HSMCI_MMCXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 150MHz,
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* CLKDIV = 2,
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* MCI_SPEED = 150MHz /(2*2 + 0 + 2) = 25 MHz
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*/
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#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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/* FLASH wait states.
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*
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* Wait states Max frequency at 105 centigrade (STH conditions)
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*
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* VDDIO
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* 1.62V 2.7V
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* --- ------- -------
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* 0 26 MHz 30 MHz
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* 1 52 MHz 62 MHz
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* 2 78 MHz 93 MHz
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* 3 104 MHz 124 MHz
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* 4 131 MHz 150 MHz
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* 5 150 MHz --- MHz
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*
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* Given: VDDIO=3.3V, VDDCORE=1.2V, MCK=150MHz
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*/
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#define BOARD_FWS 4
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/* LED definitions **********************************************************/
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/* LEDs
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*
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* There are two yellow LED available on the SAM V71 Xplained Ultra board
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* that can be turned on and off. The LEDs can be activated by driving the
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* connected I/O line to GND.
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*
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* ------ ----------- ---------------------
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* SAMV71 Function Shared functionality
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* PIO
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* ------ ----------- ---------------------
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* PA23 Yellow LED0 EDBG GPIO
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* PC09 Yellow LED1 LCD, and Shield
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* ------ ----------- ---------------------
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
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* in any way. The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED0 0
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#define BOARD_LED1 1
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#define BOARD_NLEDS 2
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED0_BIT (1 << BOARD_LED0)
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/sam_autoleds.c. The LEDs are used to encode
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* OS-related events as follows:
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*
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* SYMBOL Meaning LED state
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* LED2 LED1
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* ------------------------ -------------------------- ------ ------
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF */
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#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */
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#define LED_STACKCREATED 1 /* Idle stack created ON OFF */
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#define LED_INIRQ 2 /* In an interrupt No change */
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#define LED_SIGNAL 2 /* In a signal handler No change */
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#define LED_ASSERTION 2 /* An assertion failed No change */
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#define LED_PANIC 3 /* The system has crashed N/C Blinking */
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#undef LED_IDLE /* MCU is is sleep mode Not used */
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/* Thus if LED0 is statically on, NuttX has successfully booted and is,
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* apparently, running normally. If LED1 is flashing at approximately
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* 2Hz, then a fatal error has been detected and the system has halted.
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*
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* NOTE: That LED0 is not used after completion of booting and may
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* be used by other board-specific logic.
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*/
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/* Button definitions *******************************************************/
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/* Buttons
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*
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* SAM V71 Xplained Ultra contains three mechanical buttons. One button is
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* the RESET button connected to the SAM V71 reset line and the others are
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* generic user configurable buttons. When a button is pressed it will drive
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* the I/O line to GND.
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*
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* ------ ----------- ---------------------
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* SAMV71 Function Shared functionality
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* PIO
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* ------ ----------- ---------------------
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* RESET RESET Trace, Shield, and EDBG
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* PA09 SW0 EDBG GPIO and Camera
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* PB12 SW1 EDBG SWD and Chip Erase
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* ------ ----------- ---------------------
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*
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* NOTES:
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*
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* - There are no pull-up resistors connected to the generic user buttons
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* so it is necessary to enable the internal pull-up in the SAM V71 to
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* use the button.
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* - PB12 is set up as a system flash ERASE pin when the firmware boots. To
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* use the SW1, PB12 has to be configured as a normal regular I/O pin in
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* the MATRIX module. For more information see the SAM V71 datasheet.
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*/
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#define BUTTON_SW0 0
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#define BUTTON_SW1 1
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#define NUM_BUTTONS 2
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#define BUTTON_SW0_BIT (1 << BUTTON_SW0)
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#define BUTTON_SW1_BIT (1 << BUTTON_SW1)
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/* PIO Disambiguation *******************************************************/
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/* Serial Console
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*
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* The SAMV71-XULT has no on-board RS-232 drivers so it will be necessary
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* to use either the VCOM or an external RS-232 driver.
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* Here are some options.
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*
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* - Arduino Serial Shield: One option is to use an Arduino-compatible
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* serial shield. This will use the RXD and TXD signals available at pins
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* 0 an 1, respectively, of the Arduino "Digital Low" connector. On the
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* SAMV71-XULT board, this corresponds to UART3:
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*
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* ------ ------ ------- ------- --------
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* Pin on SAMV71 Arduino Arduino SAMV71
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* J503 PIO Name Pin Function
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* ------ ------ ------- ------- --------
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* 1 PD28 RX0 0 URXD3
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* 2 PD30 TX0 1 UTXD3
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* ------ ------ ------- ------- --------
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*
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* There are alternative pin selections only for UART3 TXD:
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*/
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#define GPIO_UART3_TXD GPIO_UART3_TXD_1
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/* - Arduino Communications. Additional UART/USART connections are available
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* on the Arduino Communications connection J505:
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*
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* ------ ------ ------- ------- --------
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* Pin on SAMV71 Arduino Arduino SAMV71
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* J503 PIO Name Pin Function
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* ------ ------ ------- ------- --------
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* 3 PD18 RX1 0 URXD4
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* 4 PD19 TX1 0 UTXD4
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* 5 PD15 RX2 0 RXD2
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* 6 PD16 TX2 0 TXD2
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* 7 PB0 RX3 0 RXD0
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* 8 PB1 TX3 1 TXD0
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* ------ ------ ------- ------- --------
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*
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* There are alternative pin selections only for UART4 TXD:
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*/
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#define GPIO_UART4_TXD GPIO_UART4_TXD_1
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/* - SAMV7-XULT EXTn connectors. USART pins are also available the EXTn
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* connectors. The following are labelled in the User Guide for USART
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* functionality:
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*
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* ---- -------- ------ --------
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* EXT1 EXTI1 SAMV71 SAMV71
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* Pin Name PIO Function
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* ---- -------- ------ --------
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* 13 USART_RX PB00 RXD0
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* 14 USART_TX PB01 TXD0
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*
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* ---- -------- ------ --------
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* EXT2 EXTI2 SAMV71 SAMV71
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* Pin Name PIO Function
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* ---- -------- ------ --------
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* 13 USART_RX PA21 RXD1
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* 14 USART_TX PB04 TXD1
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*
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* There are no alternative pin selections for USART0 or USART1.
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*/
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/* - VCOM. The Virtual Com Port gateway is available on USART1:
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*
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* ------ --------
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* SAMV71 SAMV71
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* PIO Function
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* ------ --------
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* PB04 TXD1
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* PA21 RXD1
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* ------ --------
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*
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* There are no alternative pin selections for USART1.
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*/
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/* WM8904 Audio Codec
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*
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* SAMV71 Interface WM8904 Interface
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* ---- ------------ ------- ----------------------------------
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* PIO Usage Pin Function
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* ---- ------------ ------- ----------------------------------
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* PA3 TWD0 SDA I2C control interface, data line
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* PA4 TWCK0 SCLK I2C control interface, clock line
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* PA10 RD ADCDAT Digital audio output (microphone)
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* PB18 PCK2 MCLK Master clock
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* PB0 TF LRCLK Left/right data alignment clock
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* PB1 TK BCLK Bit clock, for synchronization
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* PD11 GPIO IRQ Audio interrupt
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* PD24 RF LRCLK Left/right data alignment clock
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* PD26 TD DACDAT Digital audio input (headphone)
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* ---- ------------ ------- ----------------------------------
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*
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* SSC
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*
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* Alternative pin selections are available only for SSC0 TD.
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* On the SAMV71-XULT board, PD26 supports the I2S TD function
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*/
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#define GPIO_SSC0_TD GPIO_SSC0_TD_1
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/* maXTouch Xplained Pro Standard Extension Header **************************
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* -----------------------------------------------
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* This LCD could be connected either via EXT1 or EXT2 using the 2x10
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* 20-pin cable and the maXTouch Xplained Pro standard extension
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* header. Access is then performed in SPI mode.
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*
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* ---- -------- ---- ----------- ---- ----------- --------------------------
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* SAMV71-XULT maxTouch Xplained Pro
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* PIN FUNCTION EXT1 FUNC EXT2 FUNC Description
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* ---- -------- ---- ----------- ---- ----------- --------------------------
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* 1 ID - - - - Communication line to
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* ID chip
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* 2 GND - - - - Ground
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* 3 N/C PC31 - PD30 -
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* 4 N/C PA19 - PC13 -
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* 5 GPIO PB3 GPIO PA6 GPIO Command/Data Select
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* 6 N/C PB2 - PD11 -
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* 7 PWM PA0 PWMC0_PWMH0 PC19 PWMC0_PMWH2 Backlight control
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* 8 N/C PC30 - PD26 -
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* 9 GPIO/IRQ PD28 GPIO PA2 GPIO IRQ from
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* maXTouch controller
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* 10 GPIO PA5 GPIO PA24 GPIO RESET signal
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* 11 I2C SDA PA3 TWID0 PA3 TWID0 maXTouch I2C Data line
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* 12 I2C SCL PA4 TWICK0 PA4 TWICK0 maXTouch I2C Clock line
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* 13 N/C PB0 - PA21 -
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* 14 N/C PB1 - PB4 -
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* 15 CS PD25 GPIO PD27 GPIO CS line for LCD controller
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* 16 SPI MOSI PD21 SPI0_MOSI PD21 SPI0_MOSI SPI Data to LCD controller
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* 17 SPI MISO PD20 SPI0_MISO PD20 SPI0_MISO SPI Data from
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* LCD controller
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* 18 SPI SCK PD22 SPI0_SPCK PD22 SPI0_SPCK SPI Clock line
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* 19 GND - - - - Ground
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* 20 VCC - - - - Target supply voltage
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* ---- -------- ---- ----------- ---- ----------- --------------------------
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*
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* There are no alternatives for SPI0 and TWI0 pins.
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* Only the PWM pins require any disambiguration.
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*/
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#ifdef CONFIG_SAMV71XULT_MXTXPLND
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# if defined(CONFIG_SAMV71XULT_MXTXPLND_EXT1)
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# define GPIO_PWMC0_H0 GPIO_PWMC0_H0_1
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# define GPIO_MXTXLND_PWM GPIO_PWMC0_H0_1
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# define GPIO_SPI0_NPCS1 GPIO_SPI0_NPCS1_2
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# elif defined(CONFIG_SAMV71XULT_MXTXPLND_EXT2)
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# define GPIO_PWMC0_H2 GPIO_PWMC0_H2_5
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# define GPIO_MXTXLND_PWM GPIO_PWMC0_H2_5
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/* maXTouch Xplained Pro Xplained Pro LCD Connector *************************
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*
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* Only the parallel is supported by this BSP (via SMC/EBI).
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* The switch mode selector on the back of the maXtouch should be set in
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* the OFF-ON-OFF positions to select 16-bit color mode.
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*
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* ----------------- ------------- ------------------------------------------
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* LCD SAMV71 Description
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* Pin Function Pin Function
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* ---- ------------ ---- -------- ------------------------------------------
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* 1 ID - - Chip ID communication line
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* 2 GND - GND Ground
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* 3 D0 PC0 D0 Data line
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* 4 D1 PC1 D1 Data line
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* 5 D2 PC2 D2 Data line
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* 6 D3 PC3 D3 Data line
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* 7 GND - GND Ground
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* 8 D4 PC4 D4 Data line
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* 9 D5 PC5 D5 Data line
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* 10 D6 PC6 D6 Data line
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* 11 D7 PC7 D7 Data line
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* 12 GND - GND Ground
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* 13 D8 PE0 D8 Data line
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* 14 D9 PE1 D9 Data line
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* 15 D10 PE2 D10 Data line
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* 16 D11 PE3 D11 Data line
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* 17 GND - GND Ground
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* 18 D12 PE4 D12 Data line
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* 19 D13 PE5 D13 Data line
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* 20 D14 PA15 D14 Data line
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* 21 D15 PA16 D15 Data line
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* 22 GND - GND Ground
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* 23 D16 - - Data line
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* 24 D17 - - Data line
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* 25 N/C - -
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* 26 N/C - -
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* 27 GND - GND Ground
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* 28 N/C - -
|
|
* 29 N/C - -
|
|
* 30 N/C - -
|
|
* 31 N/C - -
|
|
* 32 GND - GND Ground
|
|
* 33 PCLK/ PC30 GPIO SMC: Pixel clock Display RAM select.
|
|
* CMD_DATA_SEL SPI: One address line of the MCU for
|
|
* displays where it is possible
|
|
* to select either the register
|
|
* or the data interface
|
|
* 34 VSYNC/CS PD19 NCS3 SMC: Vertical synchronization.
|
|
* SPI: Chip select
|
|
* 35 HSYNC/WE PC8 NWE SMC: Horizontal synchronization
|
|
* SPI: Write enable signal
|
|
* 36 DATA ENABLE/ PC11 NRD SMC: Data enable signal
|
|
* RE SPI: Read enable signal
|
|
* 37 SPI SCK - - SPI: Clock for SPI
|
|
* 38 SPI MOSI - - SPI: Master out slave in line of SPI
|
|
* 39 SPI MISO - - SPI: Master in slave out line of SPI
|
|
* 40 SPI SS - - SPI: Slave select for SPI
|
|
* 41 N/C - -
|
|
* 42 TWI SDA PA3 TWD0 I2C data line (maXTouch®)
|
|
* 43 TWI SCL PA4 TWCK0 I2C clock line (maXTouch)
|
|
* 44 IRQ1 PD28 WKUP5 maXTouch interrupt line
|
|
* 45 N/C PA2 WKUP2
|
|
* 46 PWM PC9 TIOB7 Backlight control
|
|
* 47 RESET PC13 GPIO Reset for both display and maxTouch
|
|
* 48 VCC - - 3.3V power supply for extension board
|
|
* 49 VCC - - 3.3V power supply for extension board
|
|
* 50 GND - - Ground
|
|
* ---- ------------ ---- -------- ------------------------------------------
|
|
*/
|
|
|
|
# elif defined(CONFIG_SAMV71XULT_MXTXPLND_LCD)
|
|
|
|
# define GPIO_SMC_NCS3 GPIO_SMC_NCS3_2
|
|
|
|
# endif
|
|
#endif /* CONFIG_SAMV71XULT_MXTXPLND */
|
|
|
|
/* MCAN1
|
|
*
|
|
* SAM V71 Xplained Ultra has two MCAN modules that performs communication
|
|
* according to ISO11898-1 (Bosch CAN specification 2.0 part A,B) and Bosch
|
|
* CAN FD specification V1.0.
|
|
* MCAN1 is connected to an on-board ATA6561 CAN physical-layer transceiver.
|
|
*
|
|
* ------- -------- -------- -------------
|
|
* SAM V71 FUNCTION ATA6561 SHARED
|
|
* PIN FUNCTION FUNCTIONALITY
|
|
* ------- -------- -------- -------------
|
|
* PC14 CANTX1 TXD Shield
|
|
* PC12 CANRX1 RXD Shield
|
|
* ------- -------- -------- -------------
|
|
*/
|
|
|
|
#define GPIO_MCAN1_TX GPIO_MCAN1_TX_2
|
|
#define GPIO_MCAN1_RX GPIO_MCAN1_RX_2
|
|
|
|
/****************************************************************************
|
|
* Public Types
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Public Data
|
|
****************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Public Functions Definitions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: sam_lcdclear
|
|
*
|
|
* Description:
|
|
* This is a non-standard LCD interface just for the SAM4e-EK board.
|
|
* Because of the various rotations, clearing the display in the normal
|
|
* way by writing a sequences of runs that covers the entire display can
|
|
* be very slow.
|
|
* Here the display is cleared by simply setting all GRAM memory to the
|
|
* specified color.
|
|
*
|
|
****************************************************************************/
|
|
|
|
void sam_lcdclear(uint16_t color);
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* __BOARDS_ARM_SAMV7_SAMV71_XULT_INCLUDE_BOARD_H */
|