254 lines
11 KiB
C
254 lines
11 KiB
C
/****************************************************************************
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* boards/arm/stm32/olimexino-stm32/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include "stm32_rcc.h"
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#include "stm32_sdio.h"
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#include "stm32.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* HSI - 8 MHz RC factory-trimmed
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* LSI - 40 KHz RC (30-60KHz, uncalibrated)
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* HSE - On-board crystal frequency is 8MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 8000000ul
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#define STM32_LSI_FREQUENCY 40000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* PLL source is HSE/1,
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* PLL multipler is 9:
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* PLL frequency is 8MHz (XTAL) x 9 = 72MHz
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*/
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
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#define STM32_CFGR_PLLXTPRE 0
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
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/* Use the PLL and set the SYSCLK source to be the PLL */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* AHB clock (HCLK) is SYSCLK (72MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* APB2 clock (PCLK2) is HCLK (72MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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/* APB2 timers 1 and 8 will receive PCLK2. */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB1 timers 2-7 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* USB divider -- Divide PLL clock by 1.5 */
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#define STM32_CFGR_USBPRE 0
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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/* Buttons ******************************************************************/
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#define BUTTON_BOOT0_BIT (0)
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#define BUTTON_BOOT0_MASK (1<<BUTTON_BOOT0_BIT)
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/* Leds *********************************************************************/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED2 1
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#define BOARD_LED_YELLOW BOARD_LED2
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#define BOARD_NLEDS 2
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED_GREEN_BIT (1 << BOARD_LED_GREEN)
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#define BOARD_LED_YELLOW_BIT (1 << BOARD_LED_YELLOW)
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is as follows:
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*
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* SYMBOL Meaning LED state
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* Green Yellow
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* ------------------------ -------------------------- ------ ------
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF */
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF */
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF OFF */
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#define LED_STACKCREATED 3 /* Idle stack created ON OFF */
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#define LED_INIRQ 4 /* In an interrupt N/C ON */
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#define LED_SIGNAL 5 /* In a signal handler N/C ON */
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#define LED_ASSERTION 6 /* An assertion failed N/C ON */
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#define LED_PANIC 7 /* The system has crashed N/C Blinking */
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#define LED_IDLE 8 /* MCU is is sleep mode OFF N/C */
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/* Thus if the Green is statically on, NuttX has successfully booted and is,
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* apparently, running normally. If the YellowLED is flashing at
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* approximately 2Hz, then a fatal error has been detected and the system
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* has halted.
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*
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* NOTE: That the Yellow is not used after completion of booting and may
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* be used by other board-specific logic.
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*/
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/* ADC1 */
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#define GPIO_ADC123_IN0 GPIO_ADC123_IN0_0 /* PA0 */
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#define GPIO_ADC123_IN1 GPIO_ADC123_IN1_0 /* PA1 */
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#define GPIO_ADC123_IN2 GPIO_ADC123_IN2_0 /* PA2 */
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#define GPIO_ADC123_IN3 GPIO_ADC123_IN3_0 /* PA3 */
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#define GPIO_ADC123_IN10 GPIO_ADC123_IN10_0 /* PC0 */
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#define GPIO_ADC123_IN11 GPIO_ADC123_IN11_0 /* PC1 */
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#define GPIO_ADC123_IN12 GPIO_ADC123_IN12_0 /* PC2 */
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#define GPIO_ADC123_IN13 GPIO_ADC123_IN13_0 /* PC3 */
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/* ADC1 */
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#define GPIO_ADC12_IN4 GPIO_ADC12_IN4_0 /* PA4 */
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#define GPIO_ADC12_IN5 GPIO_ADC12_IN5_0 /* PA5 */
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#define GPIO_ADC12_IN6 GPIO_ADC12_IN6_0 /* PA6 */
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#define GPIO_ADC12_IN7 GPIO_ADC12_IN7_0 /* PA7 */
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#define GPIO_ADC12_IN8 GPIO_ADC12_IN8_0 /* PB0 */
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#define GPIO_ADC12_IN9 GPIO_ADC12_IN9_0 /* PB1 */
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#define GPIO_ADC12_IN14 GPIO_ADC12_IN14_0 /* PC4 */
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#define GPIO_ADC12_IN15 GPIO_ADC12_IN15_0 /* PC5 */
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/* TIM1 */
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#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 /* PA12 */
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#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 /* PA8 */
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#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) /* PA8 */
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#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 /* PA9 */
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#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) /* PA9 */
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#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 /* PA10 */
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#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) /* PA10 */
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#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 /* PA11 */
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#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) /* PA11 */
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#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 /* PA6 */
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#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) /* PA7 */
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#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) /* PB0 */
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#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) /* PB1 */
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/* TIM3 */
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#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_0 /* PB4 */
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#define GPIO_TIM3_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH1OUT_0, GPIO_MODE_50MHz) /* PB4 */
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#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_0 /* PB5 */
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#define GPIO_TIM3_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH2OUT_0, GPIO_MODE_50MHz) /* PB5 */
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#define GPIO_TIM3_CH3IN GPIO_TIM3_CH3IN_0 /* PB0 */
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#define GPIO_TIM3_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH3OUT_0, GPIO_MODE_50MHz) /* PB0 */
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#define GPIO_TIM3_CH4IN GPIO_TIM3_CH4IN_0 /* PB1 */
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#define GPIO_TIM3_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH4OUT_0, GPIO_MODE_50MHz) /* PB1 */
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/* USART1 */
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#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) /* PA9 */
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#define GPIO_USART1_RX GPIO_USART1_RX_0 /* PA10 */
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/* USART2 */
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#define GPIO_USART2_CTS GPIO_USART2_CTS_0 /* PA0 */
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#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) /* PA1 */
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#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) /* PA2 */
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#define GPIO_USART2_RX GPIO_USART2_RX_0 /* PA3 */
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#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) /* PA4 */
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/* SPI1 */
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#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) /* PA4 */
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#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) /* PA5 */
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#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) /* PA6 */
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#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) /* PA7 */
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/* SPI2 */
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#define GPIO_SPI2_NSS GPIO_ADJUST_MODE(GPIO_SPI2_NSS_0, GPIO_MODE_50MHz) /* PB12 */
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#define GPIO_SPI2_SCK GPIO_ADJUST_MODE(GPIO_SPI2_SCK_0, GPIO_MODE_50MHz) /* PB13 */
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#define GPIO_SPI2_MISO GPIO_ADJUST_MODE(GPIO_SPI2_MISO_0, GPIO_MODE_50MHz) /* PB14 */
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#define GPIO_SPI2_MOSI GPIO_ADJUST_MODE(GPIO_SPI2_MOSI_0, GPIO_MODE_50MHz) /* PB15 */
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/* I2C2 */
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#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz) /* PB10 */
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#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz) /* PB11 */
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#define GPIO_I2C2_SMBA GPIO_ADJUST_MODE(GPIO_I2C2_SMBA_0, GPIO_MODE_50MHz) /* PB12 */
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/* CAN1 */
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#define GPIO_CAN1_RX GPIO_CAN1_RX_0 /* PB8 */
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#define GPIO_CAN1_TX GPIO_ADJUST_MODE(GPIO_CAN1_TX_0, GPIO_MODE_50MHz) /* PB9 */
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#endif /* __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H */
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