nuttx/boards/arm/stm32f0l0g0/stm32f051-discovery
Gregory Nutt 9ce03b1660 Move pthread-specific data into TLS
1. Move pthread-specific data files from sched/pthread/ to libs/libc/pthread.
2. Remove pthread-specific data functions from syscalls.
3. Implement tls_alloc() and tls_free() with system calls.
4. Reimplement pthread_key_create() and pthread_key_free() using tls_alloc() and tls_free().
5. Reimplement pthread_set_specific() and pthread_get_specicif() using tls_set_value() and tls_get_value()
2020-05-08 18:05:04 +01:00
..
configs/nsh Move pthread-specific data into TLS 2020-05-08 18:05:04 +01:00
include Refine the preprocessor conditional guard style (#190) 2020-01-31 19:07:39 +01:00
scripts Use EXTRAFLAGS instead of EXTRADEFINES to be used by make via command line 2020-04-11 08:31:08 -06:00
src arch/arm: Rename all up_*.h files to arm_*.h 2020-05-01 03:43:44 +01:00
Kconfig
README.txt

STATUS
======

05/17: The basic NSH configuration is functional and shows that there is
       3-4KB of free heap space.  However, attempts to extend this have
       failed.  I suspect that 8KB of SRAM is insufficient to do much
       with the existing NSH configuration.  Perhaps some fine tuning
       can improve this situation but at this point, I think this board
       is only useful for the initial STM32 F0 bring-up, perhaps for
       embedded solutions that do not use NSH and for general
       experimentation.

       There is also support for the Nucleo boards with the STM32 F072
       and F092 MCUs.  Those ports do not suffer from these problems and
       seem to work well in fairly complex configurations.  Apparently 8KB
       is SRAM is not usable but the parts with larger 16KB and 32KB SRAMs
       are better matches.