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Lee Lup Yuen 856526adee arch/risc-v: Add support for StarFive JH7110 SoC 
This PR adds support for the StarFive JH7110 RISC-V SoC. This will be used by the upcoming port of NuttX for PINE64 Star64 SBC. [The source files are explained in the articles here](https://github.com/lupyuen/nuttx-star64)

Modified Files in arch/risc-v:

Kconfig: Added ARCH_CHIP_JH7110 for JH7110 SoC

New Files in arch/risc-v:

include/jh7110/chip.h: JH7110 Definitions

include/jh7110/irq.h: Support 127 External Interrupts

src/jh7110/chip.h: Interrupt Stack Macro

src/jh7110/jh7110_allocateheap.c: Kernel Heap

src/jh7110/jh7110_head.S: Linux Header and Boot Code

src/jh7110/jh7110_irq.c: Configure Interrupts

src/jh7110/jh7110_irq_dispatch.c: Dispatch Interrupts

src/jh7110/jh7110_memorymap.h: Memory Map

src/jh7110/jh7110_mm_init.c, jh7110_mm_init.h: Memory Mgmt

src/jh7110/jh7110_pgalloc.c: Page Allocator

src/jh7110/jh7110_start.c: Startup Code

src/jh7110/jh7110_timerisr.c: Timer Interrupt

src/jh7110/hardware/jh7110_memorymap.h: PLIC Base Address

src/jh7110/hardware/jh7110_plic.h: PLIC Register Addresses

src/jh7110/Kconfig: JH7110 Config

src/jh7110/Make.defs: Makefile
2023-08-03 22:55:55 -07:00
..
bl602
c906
esp32c3
esp32c6
espressif arch/risc-v/espressif: Add full GPIO support 2023-06-24 13:11:45 +08:00
fe310
hpm6750
jh7110 arch/risc-v: Add support for StarFive JH7110 SoC 2023-08-03 22:55:55 -07:00
k210
litex
mpfs
qemu-rv
rv32m1
.gitignore
arch.h
barriers.h riscv/barrier: Define more granular memory barriers 2023-06-14 16:14:57 -03:00
csr.h
elf.h
inttypes.h
irq.h riscv/lazyfpu: Add option to disable lazy FPU 2023-07-31 07:48:53 -07:00
limits.h
mode.h
setjmp.h
spinlock.h
stdarg.h
syscall.h
types.h