213 lines
6.3 KiB
C
213 lines
6.3 KiB
C
/*
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* Copyright (c) 2011 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef BCMF_SDIO_CHIP_H_
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#define BCMF_SDIO_CHIP_H_
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#include <stdint.h>
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif
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/* SDIO device ID */
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#define SDIO_DEVICE_ID_BROADCOM_43143 43143
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#define SDIO_DEVICE_ID_BROADCOM_43241 0x4324
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#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
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#define SDIO_DEVICE_ID_BROADCOM_4330 0x4330
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#define SDIO_DEVICE_ID_BROADCOM_4334 0x4334
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#define SDIO_DEVICE_ID_BROADCOM_4335_4339 0x4335
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#define SDIO_DEVICE_ID_BROADCOM_43362 43362
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/*
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* Core reg address translation.
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* Both macro's returns a 32 bits byte address on the backplane bus.
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*/
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#define CORE_CC_REG(base, field) \
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(base + offsetof(struct chipcregs, field))
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#define CORE_BUS_REG(base, field) \
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(base + offsetof(struct sdpcmd_regs, field))
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#define CORE_SB(base, field) \
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(base + offsetof(struct sbconfig, field))
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#define BRCMF_MAX_CORENUM 6
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#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
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/* Target state register description */
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#define SSB_TMSLOW_RESET 0x00000001 /* Reset */
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#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
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#define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
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#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
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#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
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#define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
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#define SSB_TMSLOW_BE 0x80000000 /* BIST Enable */
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#define I_HMB_SW_MASK ( (uint32_t) 0x000000F0 )
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#define I_HMB_FRAME_IND ( 1<<6 )
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enum {
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CHIPCOMMON_CORE_ID = 0,
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DOT11MAC_CORE_ID,
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SDIOD_CORE_ID,
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WLAN_ARMCM3_CORE_ID,
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SOCSRAM_CORE_ID,
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MAX_CORE_ID
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};
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struct chip_core_info {
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uint16_t id;
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uint16_t rev;
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uint32_t base;
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uint32_t wrapbase;
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uint32_t caps;
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uint32_t cib;
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};
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struct sbconfig {
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uint8_t PAD[0xf00];
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uint32_t PAD[2];
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uint32_t sbipsflag; /* initiator port ocp slave flag */
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uint32_t PAD[3];
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uint32_t sbtpsflag; /* target port ocp slave flag */
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uint32_t PAD[11];
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uint32_t sbtmerrloga; /* (sonics >= 2.3) */
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uint32_t PAD;
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uint32_t sbtmerrlog; /* (sonics >= 2.3) */
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uint32_t PAD[3];
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uint32_t sbadmatch3; /* address match3 */
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uint32_t PAD;
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uint32_t sbadmatch2; /* address match2 */
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uint32_t PAD;
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uint32_t sbadmatch1; /* address match1 */
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uint32_t PAD[7];
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uint32_t sbimstate; /* initiator agent state */
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uint32_t sbintvec; /* interrupt mask */
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uint32_t sbtmstatelow; /* target state */
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uint32_t sbtmstatehigh; /* target state */
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uint32_t sbbwa0; /* bandwidth allocation table0 */
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uint32_t PAD;
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uint32_t sbimconfiglow; /* initiator configuration */
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uint32_t sbimconfighigh; /* initiator configuration */
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uint32_t sbadmatch0; /* address match0 */
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uint32_t PAD;
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uint32_t sbtmconfiglow; /* target configuration */
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uint32_t sbtmconfighigh; /* target configuration */
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uint32_t sbbconfig; /* broadcast configuration */
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uint32_t PAD;
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uint32_t sbbstate; /* broadcast state */
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uint32_t PAD[3];
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uint32_t sbactcnfg; /* activate configuration */
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uint32_t PAD[3];
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uint32_t sbflagst; /* current sbflags */
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uint32_t PAD[3];
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uint32_t sbidlow; /* identification */
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uint32_t sbidhigh; /* identification */
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};
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/* sdio core registers */
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struct sdpcmd_regs {
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uint32_t corecontrol; /* 0x00, rev8 */
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uint32_t corestatus; /* rev8 */
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uint32_t PAD[1];
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uint32_t biststatus; /* rev8 */
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/* PCMCIA access */
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uint16_t pcmciamesportaladdr; /* 0x010, rev8 */
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uint16_t PAD[1];
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uint16_t pcmciamesportalmask; /* rev8 */
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uint16_t PAD[1];
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uint16_t pcmciawrframebc; /* rev8 */
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uint16_t PAD[1];
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uint16_t pcmciaunderflowtimer; /* rev8 */
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uint16_t PAD[1];
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/* interrupt */
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uint32_t intstatus; /* 0x020, rev8 */
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uint32_t hostintmask; /* rev8 */
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uint32_t intmask; /* rev8 */
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uint32_t sbintstatus; /* rev8 */
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uint32_t sbintmask; /* rev8 */
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uint32_t funcintmask; /* rev4 */
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uint32_t PAD[2];
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uint32_t tosbmailbox; /* 0x040, rev8 */
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uint32_t tohostmailbox; /* rev8 */
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uint32_t tosbmailboxdata; /* rev8 */
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uint32_t tohostmailboxdata; /* rev8 */
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/* synchronized access to registers in SDIO clock domain */
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uint32_t sdioaccess; /* 0x050, rev8 */
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uint32_t PAD[3];
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/* PCMCIA frame control */
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uint8_t pcmciaframectrl; /* 0x060, rev8 */
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uint8_t PAD[3];
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uint8_t pcmciawatermark; /* rev8 */
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uint8_t PAD[155];
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/* interrupt batching control */
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uint32_t intrcvlazy; /* 0x100, rev8 */
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uint32_t PAD[3];
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/* counters */
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uint32_t cmd52rd; /* 0x110, rev8 */
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uint32_t cmd52wr; /* rev8 */
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uint32_t cmd53rd; /* rev8 */
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uint32_t cmd53wr; /* rev8 */
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uint32_t abort; /* rev8 */
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uint32_t datacrcerror; /* rev8 */
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uint32_t rdoutofsync; /* rev8 */
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uint32_t wroutofsync; /* rev8 */
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uint32_t writebusy; /* rev8 */
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uint32_t readwait; /* rev8 */
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uint32_t readterm; /* rev8 */
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uint32_t writeterm; /* rev8 */
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uint32_t PAD[40];
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uint32_t clockctlstatus; /* rev8 */
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uint32_t PAD[7];
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uint32_t PAD[128]; /* DMA engines */
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/* SDIO/PCMCIA CIS region */
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char cis[512]; /* 0x400-0x5ff, rev6 */
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/* PCMCIA function control registers */
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char pcmciafcr[256]; /* 0x600-6ff, rev6 */
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uint16_t PAD[55];
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/* PCMCIA backplane access */
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uint16_t backplanecsr; /* 0x76E, rev6 */
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uint16_t backplaneaddr0; /* rev6 */
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uint16_t backplaneaddr1; /* rev6 */
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uint16_t backplaneaddr2; /* rev6 */
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uint16_t backplaneaddr3; /* rev6 */
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uint16_t backplanedata0; /* rev6 */
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uint16_t backplanedata1; /* rev6 */
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uint16_t backplanedata2; /* rev6 */
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uint16_t backplanedata3; /* rev6 */
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uint16_t PAD[31];
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/* sprom "size" & "blank" info */
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uint16_t spromstatus; /* 0x7BE, rev2 */
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uint32_t PAD[464];
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uint16_t PAD[0x80];
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};
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#endif /* _BCMF_SDIO_CHIP_H_ */
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