1ef3767f85
Add ipi process abstract function support. Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
122 lines
5.0 KiB
C
122 lines
5.0 KiB
C
/****************************************************************************
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* arch/risc-v/include/mode.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_MODE_H
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#define __ARCH_RISCV_INCLUDE_MODE_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_ARCH_USE_S_MODE
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/* CSR definitions */
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# define CSR_STATUS CSR_SSTATUS /* Global status register */
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# define CSR_SCRATCH CSR_SSCRATCH /* Scratch register */
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# define CSR_EPC CSR_SEPC /* Exception program counter */
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# define CSR_IE CSR_SIE /* Interrupt enable register */
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# define CSR_IP CSR_SIP /* Interrupt pending register */
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# define CSR_CAUSE CSR_SCAUSE /* Interrupt cause register */
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# define CSR_TVAL CSR_STVAL /* Trap value register */
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# define CSR_TVEC CSR_STVEC /* Trap vector base addr register */
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/* In status register */
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# define STATUS_IE SSTATUS_SIE /* Global interrupt enable */
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# define STATUS_PIE SSTATUS_SPIE /* Previous interrupt enable */
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# define STATUS_PPP SSTATUS_SPPS /* Previous privilege */
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# define STATUS_SUM SSTATUS_SUM /* Access to user memory */
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/* Interrupt bits */
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# define IE_EIE SIE_SEIE /* External interrupt enable */
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# define IE_SIE SIE_SSIE /* Software interrupt enable */
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# define IE_TIE SIE_STIE /* Timer interrupt enable */
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/* Interrupt pending bits */
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# define IP_EIP SIP_SEIP /* External interrupt pending */
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# define IP_SIP SIP_SSIP /* Software interrupt pending */
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# define IP_TIP SIP_STIP /* Timer interrupt pending */
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/* External, timer and software interrupt */
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# define RISCV_IRQ_EXT RISCV_IRQ_SEXT /* PLIC IRQ */
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# define RISCV_IRQ_TIMER RISCV_IRQ_STIMER /* Timer IRQ */
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# define RISCV_IRQ_SOFT RISCV_IRQ_SSOFT /* SW IRQ */
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/* Define return from exception */
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# define ERET sret
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#else
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/* CSR definitions */
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# define CSR_STATUS CSR_MSTATUS /* Global status register */
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# define CSR_SCRATCH CSR_MSCRATCH /* Scratch register */
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# define CSR_EPC CSR_MEPC /* Exception program counter */
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# define CSR_IE CSR_MIE /* Interrupt enable register */
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# define CSR_IP CSR_MIP /* Interrupt pending register */
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# define CSR_CAUSE CSR_MCAUSE /* Interrupt cause register */
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# define CSR_TVAL CSR_MTVAL /* Trap value register */
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# define CSR_TVEC CSR_MTVEC /* Trap vector base addr register */
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/* In status register */
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# define STATUS_IE MSTATUS_MIE /* Global interrupt enable */
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# define STATUS_PIE MSTATUS_MPIE /* Previous interrupt enable */
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# define STATUS_PPP MSTATUS_MPPM /* Previous privilege */
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# define STATUS_SUM 0 /* Not needed in M-mode */
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/* Interrupt bits */
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# define IE_EIE MIE_MEIE /* External interrupt enable */
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# define IE_SIE MIE_MSIE /* Software interrupt enable */
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# define IE_TIE MIE_MTIE /* Timer interrupt enable */
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/* Interrupt pending bits */
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# define IP_EIP MIP_MEIP /* External interrupt pending */
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# define IP_SIP MIP_MSIP /* Software interrupt pending */
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# define IP_TIP MIP_MTIP /* Timer interrupt pending */
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/* External, timer and software interrupt */
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# define RISCV_IRQ_EXT RISCV_IRQ_MEXT /* PLIC IRQ */
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# define RISCV_IRQ_TIMER RISCV_IRQ_MTIMER /* Timer IRQ */
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# define RISCV_IRQ_SOFT RISCV_IRQ_MSOFT /* SW IRQ */
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/* Define return from exception */
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# define ERET mret
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#endif
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#endif /* __ARCH_RISCV_INCLUDE_MODE_H */
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