435 lines
15 KiB
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435 lines
15 KiB
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==========
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ST STM32F7
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==========
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Supported MCUs
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==============
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TODO
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Peripheral Support
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==================
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..
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Individual subsystems can be enabled:
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========================= ==========
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APB1 Peripheral
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========================= ==========
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CONFIG_STM32F7_TIM2 TIM2
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CONFIG_STM32F7_TIM3 TIM3
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CONFIG_STM32F7_TIM4 TIM4
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CONFIG_STM32F7_TIM5 TIM5
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CONFIG_STM32F7_TIM6 TIM6
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CONFIG_STM32F7_TIM7 TIM7
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CONFIG_STM32F7_TIM12 TIM12
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CONFIG_STM32F7_TIM13 TIM13
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CONFIG_STM32F7_TIM14 TIM14
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CONFIG_STM32F7_LPTIM1 LPTIM1
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CONFIG_STM32F7_RTC RTC
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CONFIG_STM32F7_BKP BKP Registers
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CONFIG_STM32F7_WWDG WWDG
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CONFIG_STM32F7_IWDG IWDG
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CONFIG_STM32F7_SPI2 SPI2
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CONFIG_STM32F7_I2S2 I2S2
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CONFIG_STM32F7_SPI3 SPI3
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CONFIG_STM32F7_I2S3 I2S3
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CONFIG_STM32F7_SPDIFRX SPDIFRX
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CONFIG_STM32F7_USART2 USART2
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CONFIG_STM32F7_USART3 USART3
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CONFIG_STM32F7_UART4 UART4
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CONFIG_STM32F7_UART5 UART5
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CONFIG_STM32F7_I2C1 I2C1
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CONFIG_STM32F7_I2C2 I2C2
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CONFIG_STM32F7_I2C3 I2C3
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CONFIG_STM32F7_I2C4 I2C4
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CONFIG_STM32F7_CAN1 CAN1
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CONFIG_STM32F7_CAN2 CAN2
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CONFIG_STM32F7_HDMICEC HDMI-CEC
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CONFIG_STM32F7_PWR PWR
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CONFIG_STM32F7_DAC DAC
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CONFIG_STM32F7_UART7 UART7
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CONFIG_STM32F7_UART8 UART8
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========================= ==========
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========================= ==========
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APB2 Peripheral
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========================= ==========
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CONFIG_STM32F7_TIM1 TIM1
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CONFIG_STM32F7_TIM8 TIM8
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CONFIG_STM32F7_USART1 USART1
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CONFIG_STM32F7_USART6 USART6
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CONFIG_STM32F7_ADC ADC1 - ADC2 - ADC3
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CONFIG_STM32F7_SDMMC1 SDMMC1
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CONFIG_STM32F7_SPI1 SPI1
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CONFIG_STM32F7_SPI4 SPI4
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CONFIG_STM32F7_SYSCFG SYSCFG
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CONFIG_STM32F7_EXTI EXTI
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CONFIG_STM32F7_TIM9 TIM9
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CONFIG_STM32F7_TIM10 TIM10
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CONFIG_STM32F7_TIM11 TIM11
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CONFIG_STM32F7_SPI5 SPI5
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CONFIG_STM32F7_SPI6 SPI6
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CONFIG_STM32F7_SAI1 SAI1
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CONFIG_STM32F7_SAI2 SAI2
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CONFIG_STM32F7_LTDC LCD-TFT
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========================= ==========
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========================= ==========
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AHB1 Peripheral
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========================= ==========
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CONFIG_STM32F7_CRC CRC
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CONFIG_STM32F7_BKPSRAM BKPSRAM
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CONFIG_STM32F7_DMA1 DMA1
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CONFIG_STM32F7_DMA2 DMA2
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CONFIG_STM32F7_ETHMAC Ethernet MAC
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CONFIG_STM32F7_DMA2D Chrom-ART (DMA2D)
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CONFIG_STM32F7_OTGHS USB OTG HS
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========================= ==========
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========================= ==========
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AHB2 Peripheral
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========================= ==========
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CONFIG_STM32F7_OTGFS USB OTG FS
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CONFIG_STM32F7_DCMI DCMI
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CONFIG_STM32F7_CRYP CRYP
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CONFIG_STM32F7_HASH HASH
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CONFIG_STM32F7_RNG RNG
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========================= ==========
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========================= ==========
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AHB3 Peripheral
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========================= ==========
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CONFIG_STM32F7_FMC FMC control registers
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CONFIG_STM32F7_QUADSPI QuadSPI Control
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========================= ==========
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Porting STM32 F4 Drivers
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========================
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The STM32F746 is very similar to the STM32 F429 and many of the drivers
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in the stm32/ directory could be ported here: ADC, BBSRAM, CAN, DAC,
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DMA2D, FLASH, I2C, IWDG, LSE, LSI, LTDC, OTGFS, OTGHS, PM, Quadrature
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Encoder, RNG, RTCC, SDMMC (was SDIO), Timer/counters, and WWDG.
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Many of these drivers would be ported very simply; many ports would just
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be a matter of copying files and some seach-and-replacement. Like:
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1. Compare the two register definitions files; make sure that the STM32
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F4 peripheral is identical (or nearly identical) to the F7
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peripheral. If so then,
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2. Copy the register definition file from the stm32/chip directory to
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the stm32f7/chip directory, making name changes as appropriate and
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updating the driver for any minor register differences.
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3. Copy the corresponding C file (and possibly a matching .h file) from
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the stm32/ directory to the stm32f7/ directory again with naming
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changes and changes for any register differences.
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4. Update the Make.defs file to include the new C file in the build.
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For other files, particularly those that use DMA, the port will be
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significantly more complex. That is because the STM32F7 has a D-Cache
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and, as a result, we need to exercise much more care to maintain cache
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coherency. There is a Wiki page discussing the issues of porting
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drivers from the stm32/ to the stm32f7/ directories here:
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https://cwiki.apache.org/confluence/display/NUTTX/Porting+Drivers+to+the+STM32+F7
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Memory
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------
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CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)::
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CONFIG_RAM_SIZE=0x00010000 (64Kb)
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CONFIG_RAM_START - The start address of installed SRAM (SRAM1)::
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CONFIG_RAM_START=0x20010000
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CONFIG_RAM_SIZE=245760
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This configurations use only SRAM1 for data storage. The heap includes
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the remainder of SRAM1. If CONFIG_MM_REGIONS=2, then SRAM2 will be
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included in the heap.
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DTCM SRAM is never included in the heap because it cannot be used for
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DMA. A DTCM allocator is available, however, so that DTCM can be
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managed with dtcm_malloc(), dtcm_free(), etc.
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In order to use FMC SRAM, the following additional things need to be
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present in the NuttX configuration file:
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CONFIG_STM32F7_FMC_SRAM - Indicates that SRAM is available via the
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FMC (as opposed to an LCD or FLASH).
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CONFIG_HEAP2_BASE - The base address of the SRAM in the FMC address space (hex)
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CONFIG_HEAP2_SIZE - The size of the SRAM in the FMC address space (decimal)
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CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
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stack. If defined, this symbol is the size of the interrupt
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stack in bytes. If not defined, the user task stacks will be
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used during interrupt handling.
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CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
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Clock
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-----
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CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
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configuration features.::
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CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
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CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation of delay loops
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TIMER
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-----
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Timer devices may be used for different purposes. One special purpose is
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to generate modulated outputs for such things as motor control. If CONFIG_STM32F7_TIMn
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is defined (as above) then the following may also be defined to indicate that
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the timer is intended to be used for pulsed output modulation, ADC conversion,
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or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
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to assign the timer (n) for used by the ADC or DAC, but then you also have to
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configure which ADC or DAC (m) it is assigned to.::
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CONFIG_STM32F7_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
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CONFIG_STM32F7_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
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CONFIG_STM32F7_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
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CONFIG_STM32F7_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
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CONFIG_STM32F7_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
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For each timer that is enabled for PWM usage, we need the following additional
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configuration settings::
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CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
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NOTE: The STM32 timers are each capable of generating different signals on
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each of the four channels with different duty cycles. That capability is
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not supported by this driver: Only one output channel per timer.
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JTAG
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----
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USART
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-----
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CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
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m (m=4,5) for the console and ttys0 (default is the USART1).
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CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
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This specific the size of the receive buffer
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CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
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being sent. This specific the size of the transmit buffer
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CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
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CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
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CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
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CONFIG_U[S]ARTn_2STOP - Two stop bits
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CAN
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---
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CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32F7_CAN1 or
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CONFIG_STM32F7_CAN2 must also be defined)
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CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs.
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CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages. Default: 8
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CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests. Default: 4
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CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
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mode for testing. The STM32 CAN driver does support loopback mode.
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CONFIG_STM32F7_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN1 is defined.
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CONFIG_STM32F7_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined.
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CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
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CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7
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CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
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dump of all CAN registers.
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SPI
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---
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CONFIG_STM32F7_SPI_INTERRUPTS - Select to enable interrupt driven SPI
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support. Non-interrupt-driven, poll-waiting is recommended if the
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interrupt rate would be to high in the interrupt driven case.
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CONFIG_STM32F7_SPIx_DMA - Use DMA to improve SPIx transfer performance.
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Cannot be used with CONFIG_STM32F7_SPI_INTERRUPT.
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DMA
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---
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CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32F7_SDIO and CONFIG_STM32F7_DMA2.
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CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. Default: Medium
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CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default: 4-bit transfer mode.
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USB
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---
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STM32 USB OTG FS Host Driver Support
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Pre-requisites::
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CONFIG_USBDEV - Enable USB device support
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CONFIG_USBHOST - Enable USB host support
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CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block
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CONFIG_STM32F7_SYSCFG - Needed
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CONFIG_SCHED_WORKQUEUE - Worker thread support is required
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Options::
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CONFIG_STM32F7_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
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Default 128 (512 bytes)
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CONFIG_STM32F7_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
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in 32-bit words. Default 96 (384 bytes)
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CONFIG_STM32F7_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
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words. Default 96 (384 bytes)
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CONFIG_STM32F7_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
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CONFIG_STM32F7_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
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want to do that?
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CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access
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debug. Depends on CONFIG_DEBUG_FEATURES.
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CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
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packets. Depends on CONFIG_DEBUG_FEATURES.
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FPU
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===
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FPU Configuration Options
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-------------------------
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There are two version of the FPU support built into the STM32 port.
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1. Non-Lazy Floating Point Register Save
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In this configuration floating point register save and restore is
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implemented on interrupt entry and return, respectively. In this
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case, you may use floating point operations for interrupt handling
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logic if necessary. This FPU behavior logic is enabled by default
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with::
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CONFIG_ARCH_FPU=y
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2. Lazy Floating Point Register Save.
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An alternative mplementation only saves and restores FPU registers only
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on context switches. This means: (1) floating point registers are not
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stored on each context switch and, hence, possibly better interrupt
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performance. But, (2) since floating point registers are not saved,
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you cannot use floating point operations within interrupt handlers.
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This logic can be enabled by simply adding the following to your .config
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file::
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CONFIG_ARCH_FPU=y
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SPI Test
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========
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The builtin SPI test facility can be enabled with the following settings::
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+CONFIG_STM32F7_SPI=y
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+CONFIG_STM32F7_SPI1=y
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+CONFIG_STM32F7_SPI2=y
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+CONFIG_STM32F7_SPI3=y
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+# CONFIG_STM32F7_SPI_INTERRUPTS is not set
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+# CONFIG_STM32F7_SPI1_DMA is not set
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+# CONFIG_STM32F7_SPI2_DMA is not set
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+# CONFIG_STM32F7_SPI3_DMA is not set
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# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
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+CONFIG_NUCLEO_SPI_TEST=y
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+CONFIG_NUCLEO_SPI_TEST_MESSAGE="Hello World"
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+CONFIG_NUCLEO_SPI1_TEST=y
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+CONFIG_NUCLEO_SPI1_TEST_FREQ=1000000
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+CONFIG_NUCLEO_SPI1_TEST_BITS=8
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+CONFIG_NUCLEO_SPI1_TEST_MODE3=y
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+CONFIG_NUCLEO_SPI2_TEST=y
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+CONFIG_NUCLEO_SPI2_TEST_FREQ=12000000
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+CONFIG_NUCLEO_SPI2_TEST_BITS=8
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+CONFIG_NUCLEO_SPI2_TEST_MODE3=y
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+CONFIG_NUCLEO_SPI3_TEST=y
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+CONFIG_NUCLEO_SPI3_TEST_FREQ=40000000
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+CONFIG_NUCLEO_SPI3_TEST_BITS=8
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+CONFIG_NUCLEO_SPI3_TEST_MODE3=y
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+CONFIG_BOARDCTL=y
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+CONFIG_NSH_ARCHINIT=y
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Development Environment
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=======================
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Either Linux or Cygwin on Windows can be used for the development environment.
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The source has been built only using the GNU toolchain (see below). Other
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toolchains will likely cause problems.
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All testing has been conducted using the GNU toolchain from ARM for Linux.
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found here https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/4.9/4.9-2015-q3-update/+download/gcc-arm-none-eabi-4_9-2015q3-20150921-linux.tar.bz2
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If you change the default toolchain, then you may also have to modify the
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PATH environment variable to include the path to the toolchain binaries.
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IDEs
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====
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NuttX is built using command-line make. It can be used with an IDE, but some
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effort will be required to create the project.
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Makefile Build
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--------------
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Under Eclipse, it is pretty easy to set up an "empty makefile project" and
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simply use the NuttX makefile to build the system. That is almost for free
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under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
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makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
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there is a lot of help on the internet).
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Basic configuration & build steps
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==================================
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A GNU GCC-based toolchain is assumed. The PATH environment variable should
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be modified to point to the correct path to the Cortex-M7 GCC toolchain (if
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different from the default in your PATH variable).
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- Configures nuttx creating .config file in the nuttx directory.::
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$ tools/configure.sh nucleo-f746zg:nsh
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- Refreshes the .config file with the latest available configurations.::
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$ make oldconfig
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- Select the features you want in the build.::
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$ make menuconfig
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- Builds NuttX with the features you selected.::
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$ make
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Supported Boards
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================
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.. toctree::
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:glob:
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:maxdepth: 1
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boards/*/*
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