a51ebeab4b
In some special chipsets, multiple CPUs may be bundled in one hardware thread cluster, which results in hartid and cpuindex not being exactly the same. The new option will decouple Scratch-based Per-CPU storage with S-Mode to distinguish the real cpu index. Signed-off-by: chao an <anchao@lixiang.com>
644 lines
16 KiB
Plaintext
644 lines
16 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_RISCV
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comment "RISC-V Options"
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choice
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prompt "RISC-V chip selection"
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default ARCH_CHIP_RISCV_CUSTOM
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config ARCH_CHIP_FE310
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bool "SiFive FE310"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ONESHOT
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select ALARM_ARCH
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---help---
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SiFive FE310 processor (E31 RISC-V Core with MAC extensions).
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config ARCH_CHIP_K210
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bool "Kendryte K210"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU if !K210_WITH_QEMU
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select ARCH_HAVE_DPFPU if !K210_WITH_QEMU
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select ARCH_HAVE_MPU
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_MISALIGN_EXCEPTION
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select ONESHOT
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select ALARM_ARCH
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---help---
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Kendryte K210 processor (RISC-V 64bit core with GC extensions)
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config ARCH_CHIP_LITEX
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bool "Enjoy Digital LITEX VEXRISCV"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_DCACHE
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_RESET
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select LIBC_FDT
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select DEVICE_TREE
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---help---
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Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
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config ARCH_CHIP_BL602
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bool "BouffaloLab BL602"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_MISALIGN_EXCEPTION
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select ONESHOT
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select ALARM_ARCH
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---help---
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BouffaloLab BL602(rv32imfc)
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config ARCH_CHIP_ESP32C3
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bool "Espressif ESP32-C3"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_C
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select ARCH_VECNOTIRQ
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RESET
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select LIBC_ARCH_ATOMIC
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select LIBC_ARCH_MEMCPY
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select LIBC_ARCH_MEMCHR
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select LIBC_ARCH_MEMCMP
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select LIBC_ARCH_MEMMOVE
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select LIBC_ARCH_MEMSET
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select LIBC_ARCH_STRCHR
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select LIBC_ARCH_STRCMP
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select LIBC_ARCH_STRCPY
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select LIBC_ARCH_STRLCPY
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select LIBC_ARCH_STRNCPY
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select LIBC_ARCH_STRLEN
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select LIBC_ARCH_STRNLEN
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select ARCH_HAVE_TEXT_HEAP
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select ARCH_HAVE_BOOTLOADER
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select ARCH_HAVE_PERF_EVENTS
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---help---
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Espressif ESP32-C3 (RV32IMC).
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config ARCH_CHIP_ESP32C3_GENERIC
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bool "ESP32-C3"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_C
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select ARCH_VECNOTIRQ
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select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_RNG
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select ARCH_HAVE_TICKLESS
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select LIBC_ARCH_ATOMIC
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select LIBC_ARCH_MEMCPY
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select LIBC_ARCH_MEMCHR
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select LIBC_ARCH_MEMCMP
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select LIBC_ARCH_MEMMOVE
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select LIBC_ARCH_MEMSET
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select LIBC_ARCH_STRCHR
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select LIBC_ARCH_STRCMP
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select LIBC_ARCH_STRCPY
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select LIBC_ARCH_STRLCPY
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select LIBC_ARCH_STRNCPY
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select LIBC_ARCH_STRLEN
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select LIBC_ARCH_STRNLEN
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select ESPRESSIF_SOC_RTC_MEM_SUPPORTED
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select ARCH_CHIP_ESPRESSIF
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---help---
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ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash memory
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config ARCH_CHIP_ESP32C6
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bool "ESP32-C6"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_VECNOTIRQ
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select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_RNG
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select ARCH_HAVE_TICKLESS
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select LIBC_ARCH_MEMCPY
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select LIBC_ARCH_MEMCHR
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select LIBC_ARCH_MEMCMP
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select LIBC_ARCH_MEMMOVE
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select LIBC_ARCH_MEMSET
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select LIBC_ARCH_STRCHR
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select LIBC_ARCH_STRCMP
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select LIBC_ARCH_STRCPY
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select LIBC_ARCH_STRLCPY
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select LIBC_ARCH_STRNCPY
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select LIBC_ARCH_STRLEN
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select LIBC_ARCH_STRNLEN
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select ESPRESSIF_SOC_RTC_MEM_SUPPORTED
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select ARCH_CHIP_ESPRESSIF
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---help---
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Espressif ESP32-C6 (RV32IMAC).
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config ARCH_CHIP_ESP32H2
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bool "ESP32-H2"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_C
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select ARCH_VECNOTIRQ
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select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_RNG
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select ARCH_HAVE_TICKLESS
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select LIBC_ARCH_ATOMIC
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select LIBC_ARCH_MEMCPY
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select LIBC_ARCH_MEMCHR
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select LIBC_ARCH_MEMCMP
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select LIBC_ARCH_MEMMOVE
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select LIBC_ARCH_MEMSET
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select LIBC_ARCH_STRCHR
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select LIBC_ARCH_STRCMP
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select LIBC_ARCH_STRCPY
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select LIBC_ARCH_STRLCPY
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select LIBC_ARCH_STRNCPY
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select LIBC_ARCH_STRLEN
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select LIBC_ARCH_STRNLEN
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select ESPRESSIF_ESPTOOLPY_NO_STUB
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select ESPRESSIF_SOC_RTC_MEM_SUPPORTED
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select ARCH_CHIP_ESPRESSIF
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---help---
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Espressif ESP32-H2 (RV32IMC).
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config ARCH_CHIP_C906
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bool "THEAD C906"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MPU
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select ONESHOT
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select ALARM_ARCH
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---help---
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THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
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config ARCH_CHIP_MPFS
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bool "MicroChip Polarfire (MPFS)"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MPU
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select ARCH_MMU_TYPE_SV39
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_HAVE_RESET
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select ARCH_HAVE_SPI_CS_CONTROL
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select ARCH_HAVE_PWM_MULTICHAN
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select ARCH_HAVE_S_MODE
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select ONESHOT
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select ALARM_ARCH
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---help---
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MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).
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config ARCH_CHIP_RV32M1
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bool "NXP RV32M1"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_C
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---help---
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NXP RV32M1 processor (RISC-V Core with PULP extensions).
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config ARCH_CHIP_QEMU_RV
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bool "QEMU RV"
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_MPU
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select ARCH_MMU_TYPE_SV39 if ARCH_CHIP_QEMU_RV64
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select ARCH_MMU_TYPE_SV32 if ARCH_CHIP_QEMU_RV32
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_HAVE_S_MODE
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select ARCH_HAVE_ELF_EXECUTABLE
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select ONESHOT
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select ALARM_ARCH
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---help---
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QEMU Generic RV32/RV64 processor
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config ARCH_CHIP_HPM6000
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bool "Hpmicro HPM6000"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ONESHOT
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select ALARM_ARCH
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---help---
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Hpmicro HPM6000 processor (D45 RISC-V Core with MAC extensions).
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config ARCH_CHIP_HPM6750
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bool "Hpmicro HPM6750"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ONESHOT
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select ALARM_ARCH
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---help---
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Hpmicro HPM6750 processor (D45 RISC-V Core with MAC extensions).
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config ARCH_CHIP_JH7110
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bool "StarFive JH7110"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_MPU
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select ARCH_MMU_TYPE_SV39
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_HAVE_S_MODE
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select ONESHOT
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select ALARM_ARCH
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---help---
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StarFive JH7110 SoC.
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config ARCH_CHIP_BL808
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bool "Bouffalo Lab BL808"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_MPU
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select ARCH_MMU_TYPE_SV39
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_HAVE_S_MODE
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select ONESHOT
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select ALARM_ARCH
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---help---
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Bouffalo Lab BL808 SoC.
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config ARCH_CHIP_K230
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bool "Kendryte K230"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MISALIGN_EXCEPTION
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select ARCH_HAVE_MPU
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select ARCH_HAVE_ADDRENV
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select ARCH_HAVE_RESET
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select ARCH_HAVE_S_MODE
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select ARCH_HAVE_ELF_EXECUTABLE
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select ARCH_MMU_TYPE_SV39
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select ARCH_NEED_ADDRENV_MAPPING
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select NUTTSBI_LATE_INIT if NUTTSBI
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select ONESHOT
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select ALARM_ARCH
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---help---
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Kendryte K230 SoC (RV64GCV and RV64GCVX C908 cores).
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config ARCH_CHIP_RISCV_CUSTOM
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bool "Custom RISC-V chip"
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select ARCH_CHIP_CUSTOM
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---help---
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Select this option if there is no directory for the chip under arch/risc-v/src/.
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endchoice # RISC-V chip selection
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config ARCH_RV32
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bool
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default n
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config ARCH_RV64
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bool
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default n
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select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
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config ARCH_RV_ISA_M
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bool
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default n
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config ARCH_RV_ISA_A
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bool
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default n
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select ARCH_HAVE_TESTSET
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config ARCH_RV_ISA_C
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bool
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default n
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config ARCH_RV_ISA_V
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bool
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default n
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depends on ARCH_FPU
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if ARCH_RV_ISA_V
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config ARCH_RV_VECTOR_BYTE_LENGTH
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int "Vector Register Length in bytes"
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default 32
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---help---
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Predefined vector register length. If CSR vlenb is greater than the
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current reserved value, appropriate memory will be allocated to
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save/restore the vector registers.
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The XLEN-bit-wide read-only CSR vlenb holds the value VLEN/8, i.e.,
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the vector register length in bytes. The value in vlenb is a
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design-time constant in any implementation. Without this CSR, several
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instructions are needed to calculate VLEN in bytes. The code has to
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disturb current vl and vtype settings which require them to be saved and restored.
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endif
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config ARCH_RV_ISA_ZICSR_ZIFENCEI
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bool
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default y
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---help---
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https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
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https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd
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GCC-12.1.0 bumped the default ISA spec to the newer 20191213 version,
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which moves some instructions from the I extension to the Zicsr and
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Zifencei extensions. This requires explicitly specifying Zicsr and
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Zifencei when GCC >= 12.1.0. To make life easier, and avoid forcing
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toolchains that default to a newer ISA spec to version 2.2. For
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clang < 17 or GCC < 11.3.0, for which this is not possible or need
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special treatment.
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config ARCH_RV_EXPERIMENTAL_EXTENSIONS
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string "LLVM RISC-V Experimental Extensions"
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default ""
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depends on RISCV_TOOLCHAIN_CLANG
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---help---
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This option allows the platform to enable experimental extensions,
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LLVM supports (to various degrees) a number of experimental extensions.
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All experimental extensions have experimental- as a prefix. There is
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explicitly no compatibility promised between versions of the toolchain,
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and regular users are strongly advised not to make use of experimental
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extensions before they reach ratification.
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config ARCH_RV_ISA_VENDOR_EXTENSIONS
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string "Vendor Custom RISC-V Instruction Set Architecture Extensions"
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default ""
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---help---
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This option allows the platform to enable some vendor-customized ISA extensions,
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E.g OpenHW, SiFive, T-Head.
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SiFive Intelligence Extensions:
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SiFive Vector Coprocessor Interface(VCIX): xsfvcp
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SiFive FP32-to-int8 Ranged Clip Instructions: Xsfvfnrclipxfqf
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SiFive Matrix Multiply Accumulate Instructions: Xsfvfwmaccqqq
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SiFive Int8 Matrix Multiplication Instructions: XSFvqmaccqoq
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Command Line:
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xsfvcp0p1_xsfvfnrclipxfqf0p1_xsfvfwmaccqqq0p1_xsfvqmaccqoq0p1
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config ARCH_RV_MMIO_BITS
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int
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# special cases
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default 32 if ARCH_CHIP_K230
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# general fallbacks
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default 32 if ARCH_RV32
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default 64 if ARCH_RV64
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config ARCH_FAMILY
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string
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default "rv32" if ARCH_RV32
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default "rv64" if ARCH_RV64
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config ARCH_CHIP
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string
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default "fe310" if ARCH_CHIP_FE310
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default "k210" if ARCH_CHIP_K210
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default "litex" if ARCH_CHIP_LITEX
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default "bl602" if ARCH_CHIP_BL602
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default "esp32c3-legacy" if ARCH_CHIP_ESP32C3
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default "esp32c3" if ARCH_CHIP_ESP32C3_GENERIC
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default "esp32c6" if ARCH_CHIP_ESP32C6
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default "esp32h2" if ARCH_CHIP_ESP32H2
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default "c906" if ARCH_CHIP_C906
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default "mpfs" if ARCH_CHIP_MPFS
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default "rv32m1" if ARCH_CHIP_RV32M1
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default "qemu-rv" if ARCH_CHIP_QEMU_RV
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default "hpm6000" if ARCH_CHIP_HPM6000
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default "hpm6750" if ARCH_CHIP_HPM6750
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default "jh7110" if ARCH_CHIP_JH7110
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default "bl808" if ARCH_CHIP_BL808
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default "k230" if ARCH_CHIP_K230
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config ARCH_RISCV_INTXCPT_EXTENSIONS
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bool "RISC-V Integer Context Extensions"
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default n
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depends on RV32M1_OPENISA_TOOLCHAIN
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---help---
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RISC-V could be customized with extensions. Some Integer Context
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Registers have to be saved and restored when Contexts switch.
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if ARCH_RISCV_INTXCPT_EXTENSIONS
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config ARCH_RISCV_INTXCPT_EXTREGS
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int "Number of Extral RISC-V Integer Context Registers"
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default 0
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endif
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config ARCH_MMU_TYPE_SV39
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bool
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default n
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select ARCH_HAVE_MMU
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config ARCH_MMU_TYPE_SV32
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bool
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default n
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select ARCH_HAVE_MMU
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config ARCH_HAVE_S_MODE
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bool
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default n
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config ARCH_HAVE_MISALIGN_EXCEPTION
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bool
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default n
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---help---
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The chip will raise a exception while misaligned memory access.
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config RISCV_MISALIGNED_HANDLER
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bool "Software misaligned memory access handler"
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depends on ARCH_HAVE_MISALIGN_EXCEPTION
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default y
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config RISCV_PERCPU_SCRATCH
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|
bool "Enable Scratch-based Per-CPU storage"
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|
default n
|
|
---help---
|
|
In some special chipsets, multiple CPUs may be bundled in one hardware
|
|
thread cluster, which results in hartid and cpuindex not being exactly
|
|
the same.
|
|
This option will enable Scratch-based Per-CPU storage to distinguish
|
|
the real cpu index.
|
|
|
|
# Option to run NuttX in supervisor mode. This is obviously not usable in
|
|
# flat mode, is questionable in protected mode, but is mandatory in kernel
|
|
# mode.
|
|
#
|
|
# Kernel mode requires this as M-mode uses flat addressing and the kernel
|
|
# memory must be mapped in order to share memory between the kernel and
|
|
# different user tasks which reside in virtual memory.
|
|
#
|
|
# Note that S-mode requires a companion software (SBI)
|
|
#
|
|
|
|
config ARCH_USE_S_MODE
|
|
bool "Run the NuttX kernel in S-mode"
|
|
default n
|
|
depends on ARCH_HAVE_S_MODE && BUILD_KERNEL && ARCH_USE_MMU
|
|
select RISCV_PERCPU_SCRATCH
|
|
---help---
|
|
Most of the RISC-V implementations run in M-mode (flat addressing)
|
|
and/or U-mode (in case of separate kernel-/userspaces). This provides
|
|
an option to run the kernel in S-mode, if the target supports it.
|
|
|
|
choice
|
|
prompt "Toolchain Selection"
|
|
default RISCV_TOOLCHAIN_GNU_RV64
|
|
|
|
config RISCV_TOOLCHAIN_GNU_RV64
|
|
bool "Generic GNU RV64 toolchain"
|
|
select ARCH_TOOLCHAIN_GNU
|
|
---help---
|
|
This option should work for any modern GNU toolchain (GCC 5.2 or newer)
|
|
configured for riscv64-unknown-elf.
|
|
|
|
config RISCV_TOOLCHAIN_GNU_RV32
|
|
bool "Generic GNU RV32 toolchain"
|
|
select ARCH_TOOLCHAIN_GNU
|
|
---help---
|
|
This option should work for any modern GNU toolchain (GCC 5.2 or newer)
|
|
configured for riscv32-unknown-elf.
|
|
|
|
config RISCV_TOOLCHAIN_CLANG
|
|
bool "LLVM Clang toolchain"
|
|
select ARCH_TOOLCHAIN_CLANG
|
|
|
|
endchoice # Toolchain Selection
|
|
|
|
config RISCV_SEMIHOSTING_HOSTFS
|
|
bool "Semihosting HostFS"
|
|
depends on FS_HOSTFS
|
|
---help---
|
|
Mount HostFS through semihosting.
|
|
|
|
This doesn't support some directory operations like readdir because
|
|
of the limitations of semihosting mechanism.
|
|
|
|
if RISCV_SEMIHOSTING_HOSTFS
|
|
|
|
config RISCV_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
|
|
bool "Cache coherence in semihosting hostfs"
|
|
depends on ARCH_DCACHE
|
|
---help---
|
|
Flush & Invalidte cache before & after bkpt instruction.
|
|
|
|
endif # RISCV_SEMIHOSTING_HOSTFS
|
|
|
|
if ARCH_CHIP_LITEX
|
|
|
|
choice
|
|
prompt "LITEX Core Selection"
|
|
default LITEX_CORE_VEXRISCV
|
|
|
|
config LITEX_CORE_VEXRISCV
|
|
bool "vexriscv core"
|
|
|
|
config LITEX_CORE_VEXRISCV_SMP
|
|
bool "vexriscv_smp core"
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_RV_ISA_C
|
|
select ARCH_MMU_TYPE_SV32
|
|
select ARCH_HAVE_ADDRENV
|
|
select ARCH_NEED_ADDRENV_MAPPING
|
|
select ARCH_HAVE_S_MODE
|
|
select ARCH_HAVE_ELF_EXECUTABLE
|
|
|
|
endchoice # LITEX Core Selection
|
|
|
|
endif # ARCH_CHIP_LITEX
|
|
|
|
source "arch/risc-v/src/opensbi/Kconfig"
|
|
source "arch/risc-v/src/nuttsbi/Kconfig"
|
|
|
|
if ARCH_CHIP_FE310
|
|
source "arch/risc-v/src/fe310/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_K210
|
|
source "arch/risc-v/src/k210/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_LITEX
|
|
source "arch/risc-v/src/litex/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_BL602
|
|
source "arch/risc-v/src/bl602/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_ESP32C3
|
|
source "arch/risc-v/src/esp32c3-legacy/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_ESP32C3_GENERIC
|
|
source "arch/risc-v/src/esp32c3/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_ESP32C6
|
|
source "arch/risc-v/src/esp32c6/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_ESP32H2
|
|
source "arch/risc-v/src/esp32h2/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_C906
|
|
source "arch/risc-v/src/c906/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_MPFS
|
|
source "arch/risc-v/src/mpfs/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_RV32M1
|
|
source "arch/risc-v/src/rv32m1/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_QEMU_RV
|
|
source "arch/risc-v/src/qemu-rv/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_HPM6000
|
|
source "arch/risc-v/src/hpm6000/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_HPM6750
|
|
source "arch/risc-v/src/hpm6750/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_JH7110
|
|
source "arch/risc-v/src/jh7110/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_BL808
|
|
source "arch/risc-v/src/bl808/Kconfig"
|
|
endif
|
|
if ARCH_CHIP_K230
|
|
source "arch/risc-v/src/k230/Kconfig"
|
|
endif
|
|
endif # ARCH_RISCV
|