296 lines
11 KiB
C
296 lines
11 KiB
C
/****************************************************************************
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* boards/arm/samv7/samv71-xult/src/sam_sdram.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "sam_periphclks.h"
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#include "hardware/sam_memorymap.h"
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#include "hardware/sam_pinmap.h"
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#include "hardware/sam_pmc.h"
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#include "hardware/sam_matrix.h"
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#include "hardware/sam_sdramc.h"
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#include "samv71-xult.h"
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#ifdef CONFIG_SAMV7_SDRAMC
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define SDRAM_BA0 (1 << 20)
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#define SDRAM_BA1 (1 << 21)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: sam_sdram_config
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*
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* Description:
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* Configures the on-board SDRAM. SAMV71 Xplained Ultra features one
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* external IS42S16100E-7BLI, 512Kx16x2, 10ns, SDRAM. SDRAM0 is connected
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* to chip select NCS1.
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*
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* Input Parameters:
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* None
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*
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* Assumptions:
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* This test runs early in initialization before I- and D-caches are
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* enabled.
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*
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* NOTE: Since the delay loop is calibrate with caches in enabled, the
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* calls to up_udelay() are wrong ty orders of magnitude.
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*
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****************************************************************************/
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void sam_sdram_config(void)
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{
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volatile uint8_t *psdram = (uint8_t *)SAM_SDRAMCS_BASE;
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uint32_t regval;
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int i;
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/* Configure SDRAM pins */
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sam_configgpio(GPIO_SMC_D0);
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sam_configgpio(GPIO_SMC_D1);
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sam_configgpio(GPIO_SMC_D2);
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sam_configgpio(GPIO_SMC_D3);
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sam_configgpio(GPIO_SMC_D4);
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sam_configgpio(GPIO_SMC_D5);
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sam_configgpio(GPIO_SMC_D6);
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sam_configgpio(GPIO_SMC_D7);
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sam_configgpio(GPIO_SMC_D8);
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sam_configgpio(GPIO_SMC_D9);
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sam_configgpio(GPIO_SMC_D10);
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sam_configgpio(GPIO_SMC_D11);
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sam_configgpio(GPIO_SMC_D12);
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sam_configgpio(GPIO_SMC_D13);
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sam_configgpio(GPIO_SMC_D14);
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sam_configgpio(GPIO_SMC_D15);
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/* SAMV71 SDRAM
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* --------------- -----------
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* PC20 A2 A0
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* PC21 A3 A1
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* PC22 A4 A2
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* PC23 A5 A3
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* PC24 A6 A4
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* PC25 A7 A5
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* PC26 A8 A6
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* PC27 A9 A7
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* PC28 A10 A8
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* PC29 A11 A9
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* PD13 SDA10 A10
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* PA20 BA0 A11
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* PD17 CAS nCAS
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* PD14 SDCKE CKE
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* PD23 SDCK CLK
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* PC15 SDCS nCS
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* PC18 A0/NBS0 LDQM
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* PD16 RAS nRAS
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* PD15 NWR1/NBS1 UDQM
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* PD29 SDWE nWE
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*/
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sam_configgpio(GPIO_SMC_A2); /* PC20 A2 -> A0 */
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sam_configgpio(GPIO_SMC_A3); /* PC21 A3 -> A1 */
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sam_configgpio(GPIO_SMC_A4); /* PC22 A4 -> A2 */
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sam_configgpio(GPIO_SMC_A5); /* PC23 A5 -> A3 */
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sam_configgpio(GPIO_SMC_A6); /* PC24 A6 -> A4 */
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sam_configgpio(GPIO_SMC_A7); /* PC25 A7 -> A5 */
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sam_configgpio(GPIO_SMC_A8); /* PC26 A8 -> A6 */
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sam_configgpio(GPIO_SMC_A9); /* PC27 A9 -> A7 */
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sam_configgpio(GPIO_SMC_A10); /* PC28 A10 -> A8 */
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sam_configgpio(GPIO_SMC_A11); /* PC29 A11 -> A9 */
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sam_configgpio(GPIO_SDRAMC_A10_2); /* PD13 SDA10 -> A10 */
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sam_configgpio(GPIO_SDRAMC_BA0); /* PA20 BA0 -> A11 */
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sam_configgpio(GPIO_SDRAMC_CKE); /* PD14 SDCKE -> CKE */
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sam_configgpio(GPIO_SDRAMC_CK); /* PD23 SDCK -> CLK */
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sam_configgpio(GPIO_SDRAMC_CS_1); /* PC15 SDCS -> nCS */
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sam_configgpio(GPIO_SDRAMC_RAS); /* PD16 RAS -> nRAS */
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sam_configgpio(GPIO_SDRAMC_CAS); /* PD17 CAS -> nCAS */
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sam_configgpio(GPIO_SDRAMC_WE); /* PD29 SDWE -> nWE */
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sam_configgpio(GPIO_SMC_NBS0); /* PC18 A0/NBS0 -> LDQM */
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sam_configgpio(GPIO_SMC_NBS1); /* PD15 NWR1/NBS1 -> UDQM */
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/* Enable the SDRAMC peripheral */
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sam_sdramc_enableclk();
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regval = getreg32(SAM_MATRIX_CCFG_SMCNFCS);
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regval |= MATRIX_CCFG_SMCNFCS_SDRAMEN;
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putreg32(regval, SAM_MATRIX_CCFG_SMCNFCS);
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/* 1. SDRAM features must be set in the configuration register:
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* asynchronous timings (TRC, TRAS, etc.), number of columns, rows, CAS
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* latency, and the data bus width.
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*
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* SDRAMC_CR_NC_COL8 8 column bits
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* SDRAMC_CR_NR_ROW11 1 row bits
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* SDRAMC_CR_NB_BANK2 2 banks
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* SDRAMC_CR_CAS_LATENCY3 3 cycle CAS latency
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* SDRAMC_CR_DBW 16 bit
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* SDRAMC_CR_TWR(4) 4 cycle write recovery delay
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* SDRAMC_CR_TRCTRFC(11) 63 ns min
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* SDRAMC_CR_TRP(5) 21 ns min Command period (PRE to ACT)
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* SDRAMC_CR_TRCD(5) 21 ns min Active Command to read/Write
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* Command delay time
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* SDRAMC_CR_TRAS(8) 42 ns min Command period (ACT to PRE)
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* SDRAMC_CR_TXSR(13) 70 ns min Exit self-refresh to active time
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*/
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regval = SDRAMC_CR_NC_COL8 | /* 8 column bits */
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SDRAMC_CR_NR_ROW11 | /* 11 row bits */
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SDRAMC_CR_NB_BANK2 | /* 2 banks */
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SDRAMC_CR_CAS_LATENCY3 | /* 3 cycle CAS latency */
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SDRAMC_CR_DBW | /* 16 bit */
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SDRAMC_CR_TWR(4) | /* 4 cycle write recovery delay */
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SDRAMC_CR_TRCTRFC(11) | /* 63 ns min */
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SDRAMC_CR_TRP(5) | /* 21 ns min Command period (PRE to ACT) */
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SDRAMC_CR_TRCD(5) | /* 21 ns min Active Command to read/Write Command delay time */
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SDRAMC_CR_TRAS(8) | /* 42 ns min Command period (ACT to PRE) */
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SDRAMC_CR_TXSR(13); /* 70 ns min Exit self-refresh to active time */
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putreg32(regval, SAM_SDRAMC_CR);
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/* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive
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* strength (DS) and partial array self refresh (PASR) must be set in
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* the Low Power Register.
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*/
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putreg32(0, SAM_SDRAMC_LPR);
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/* 3. The SDRAM memory type must be set in the Memory Device Register. */
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putreg32(SDRAMC_MDR_SDRAM, SAM_SDRAMC_MDR);
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/* 4. A minimum pause of 200 usec is provided to precede any signal
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* toggle.
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*/
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up_udelay(200);
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/* 5. A NOP command is issued to the SDRAM devices. The application must
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* set Mode to 1 in the Mode Register and perform a write access to any
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* SDRAM address.
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*/
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putreg32(SDRAMC_MR_MODE_NOP, SAM_SDRAMC_MR);
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*psdram = 0;
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up_udelay(200);
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/* 6. An All Banks Precharge command is issued to the SDRAM devices. The
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* application must set Mode to 2 in the Mode Register and perform a
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* write access to any SDRAM address.
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*/
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putreg32(SDRAMC_MR_MODE_PRECHARGE, SAM_SDRAMC_MR);
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*psdram = 0;
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up_udelay(200);
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/* 7. Eight auto-refresh (CBR) cycles are provided. The application must
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* set the Mode to 4 in the Mode Register and perform a write access to
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* any SDRAM location eight times.
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*/
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for (i = 0 ; i < 8; i++)
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{
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putreg32(SDRAMC_MR_MODE_AUTOREFRESH, SAM_SDRAMC_MR);
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*psdram = 0;
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}
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up_udelay(200);
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/* 8. A Mode Register set (MRS) cycle is issued to program the parameters
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* of the SDRAM devices, in particular CAS latency and burst length.
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* The application must set Mode to 3 in the Mode Register and perform
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* a write access to the SDRAM. The write address must be chosen so
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* that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM
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* (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access
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* should be done at the address 0x70000000.
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*/
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putreg32(SDRAMC_MR_MODE_LOADMODE, SAM_SDRAMC_MR);
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*psdram = 0;
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up_udelay(200);
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/* 9. For mobile SDRAM initialization, an Extended Mode Register set
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* (EMRS) cycle is issued to program the SDRAM parameters (TCSR, PASR,
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* DS). The application must set Mode to 5 in the Mode Register and
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* perform a write access to the SDRAM. The write address must be
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* chosen so that BA[1] or BA[0] are set to 1.
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*
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* For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4
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* banks) bank address the SDRAM write access should be done at the
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* address 0x70800000 or 0x70400000.
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*/
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/* putreg32(SDRAMC_MR_MODE_EXTLOADMODE, SDRAMC_MR_MODE_EXT_LOAD_MODEREG);
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* *((uint8_t *)(psdram + SDRAM_BA0)) = 0;
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*/
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/* 10. The application must go into Normal Mode, setting Mode to 0 in the
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* Mode Register and performing a write access at any location in the
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* SDRAM.
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*/
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putreg32(SDRAMC_MR_MODE_NORMAL, SAM_SDRAMC_MR);
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*psdram = 0;
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up_udelay(200);
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/* 11. Write the refresh rate into the count field in the SDRAMC Refresh
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* Timer register. (Refresh rate = delay between refresh cycles). The
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* SDRAM device requires a refresh every 15.625 usec or 7.81 usec. With
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* a 100 MHz frequency, the Refresh Timer Counter Register must be set
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* with the value 1562(15.625 usec x 100 MHz) or 781(7.81 usec x 100
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* MHz).
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*
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* For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 usec
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*/
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regval = (32 * (BOARD_MCK_FREQUENCY / 1000)) / 2048 ;
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putreg32(regval, SAM_SDRAMC_TR);
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regval = getreg32(SAM_SDRAMC_CFR1);
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regval |= SDRAMC_CFR1_UNAL;
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putreg32(regval, SAM_SDRAMC_CFR1);
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/* After initialization, the SDRAM devices are fully functional. */
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}
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#endif /* CONFIG_SAMV7_SDRAMC */
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