a5bcb2dc46
Multiple files were badly formatted, which resulted in many warnings. This made it harder to check for errors in newly written documentation. What's worse, badly formatted text resulted in butchered output in generated html. This patch fixes most of the errors, but alas, not all of the errors can be fixed. Anyway, this should be way easier to spot errors in newly written docs now. Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
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===============
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Espressif ESP32
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===============
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The ESP32 is a series of single and dual-core SoCs from Espressif
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based on Harvard architecture Xtensa LX6 CPUs and with on-chip support
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for Bluetooth and Wi-Fi.
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All embedded memory, external memory and peripherals are located on the
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data bus and/or the instruction bus of these CPUs. With some minor
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exceptions, the address mapping of two CPUs is symmetric, meaning they
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use the same addresses to access the same memory. Multiple peripherals in
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the system can access embedded memory via DMA.
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On dual-core SoCs, the two CPUs are typically named "PRO_CPU" and "APP_CPU"
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(for "protocol" and "application"), however for most purposes the
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two CPUs are interchangeable.
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Toolchain
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=========
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You can use the prebuilt `toolchain <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/tools/idf-tools.html#xtensa-esp32-elf>`__
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for Xtensa architecture and `OpenOCD <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/tools/idf-tools.html#openocd-esp32>`__
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for ESP32 by Espressif.
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For flashing firmware, you will need to install ``esptool.py`` by running::
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$ pip install esptool
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Building from source
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--------------------
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You can also build the toolchain yourself. The steps to
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build the toolchain with crosstool-NG on Linux are as follows
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.. code-block:: console
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$ git clone https://github.com/espressif/crosstool-NG.git
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$ cd crosstool-NG
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$ git checkout esp-2021r1
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$ git submodule update --init
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$ ./bootstrap && ./configure --enable-local && make
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$ ./ct-ng xtensa-esp32-elf
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$ ./ct-ng build
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$ chmod -R u+w builds/xtensa-esp32-elf
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$ export PATH="crosstool-NG/builds/xtensa-esp32-elf/bin:$PATH"
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These steps are given in the setup guide in
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`ESP-IDF documentation <https://docs.espressif.com/projects/esp-idf/en/latest/get-started/linux-setup-scratch.html>`_.
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Flashing
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========
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Firmware for ESP32 is flashed via the USB/UART interface using the ``esptool.py`` tool.
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It's a two step process where the first converts the ELF file into a ESP32-compatible binary
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and the second flashes it to the board. These steps are included into the build system and you can
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flash your NuttX firmware simply by running::
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$ make flash ESPTOOL_PORT=<port>
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where ``<port>`` is typically ``/dev/ttyUSB0`` or similar. You can change the baudrate by passing ``ESPTOOL_BAUD``.
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Bootloader and partitions
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-------------------------
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ESP32 requires a bootloader to be flashed as well as a set of FLASH partitions. This is only needed the first time
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(or any time you which to modify either of these). An easy way is to use prebuilt binaries for NuttX `from here <https://github.com/espressif/esp-nuttx-bootloader>`_. In there you will find instructions to rebuild these if necessary.
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Once you downloaded both binaries, you can flash them by adding an ``ESPTOOL_BINDIR`` parameter, pointing to the directory where these binaries were downloaded:
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.. code-block:: console
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$ make flash ESPTOOL_PORT=<port> ESPTOOL_BINDIR=<dir>
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.. note:: It is recommended that if this is the first time you are using the board with NuttX that you perform a complete
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SPI FLASH erase.
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.. code-block:: console
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$ esptool.py erase_flash
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Peripheral Support
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==================
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The following list indicates the state of peripherals' support in NuttX:
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========== ======= =====
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Peripheral Support NOTES
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========== ======= =====
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GPIO Yes
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UART Yes
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SPI Yes
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I2C Yes
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DMA Yes
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Wifi Yes
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Ethernet Yes
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SPIFLASH Yes
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SPIRAM Yes
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Timers Yes
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Watchdog Yes
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RTC Yes
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RNG Yes
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AES Yes
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eFuse Yes
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ADC No
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Bluetooth Yes
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SDIO No
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SD/MMC No
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I2S No
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LED_PWM No
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RMT No
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MCPWM No
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Pulse_CNT No
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SHA No
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RSA No
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========== ======= =====
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Memory Map
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==========
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Address Mapping
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---------------
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================== ========== ========== =============== ===============
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BUS TYPE START LAST DESCRIPTION NOTES
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================== ========== ========== =============== ===============
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0x00000000 0x3F3FFFFF Reserved
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Data 0x3F400000 0x3F7FFFFF External Memory
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Data 0x3F800000 0x3FBFFFFF External Memory
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0x3FC00000 0x3FEFFFFF Reserved
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Data 0x3FF00000 0x3FF7FFFF Peripheral
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Data 0x3FF80000 0x3FFFFFFF Embedded Memory
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Instruction 0x40000000 0x400C1FFF Embedded Memory
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Instruction 0x400C2000 0x40BFFFFF External Memory
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. 0x40C00000 0x4FFFFFFF Reserved
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Data / Instruction 0x50000000 0x50001FFF Embedded Memory
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. 0x50002000 0xFFFFFFFF Reserved
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================== ========== ========== =============== ===============
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Embedded Memory
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---------------
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=========== ========== ========== =============== ===============
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BUS TYPE START LAST DESCRIPTION NOTES
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=========== ========== ========== =============== ===============
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Data 0x3ff80000 0x3ff81fff RTC FAST Memory PRO_CPU Only
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. 0x3ff82000 0x3ff8ffff Reserved
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Data 0x3ff90000 0x3ff9ffff Internal ROM 1
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. 0x3ffa0000 0x3ffadfff Reserved
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Data 0x3ffae000 0x3ffdffff Internal SRAM 2 DMA
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Data 0x3ffe0000 0x3fffffff Internal SRAM 1 DMA
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=========== ========== ========== =============== ===============
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Boundary Address (Embedded)
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---------------------------
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====================== ========== ========== =============== ===============
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BUS TYPE START LAST DESCRIPTION NOTES
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====================== ========== ========== =============== ===============
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Instruction 0x40000000 0x40007fff Internal ROM 0 Remap
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Instruction 0x40008000 0x4005ffff Internal ROM 0
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. 0x40060000 0x4006ffff Reserved
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Instruction 0x40070000 0x4007ffff Internal SRAM 0 Cache
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Instruction 0x40080000 0x4009ffff Internal SRAM 0
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Instruction 0x400a0000 0x400affff Internal SRAM 1
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Instruction 0x400b0000 0x400b7FFF Internal SRAM 1 Remap
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Instruction 0x400b8000 0x400bffff Internal SRAM 1
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Instruction 0x400c0000 0x400c1FFF RTC FAST Memory PRO_CPU Only
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Data / Instruction 0x50000000 0x50001fff RTC SLOW Memory
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====================== ========== ========== =============== ===============
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External Memory
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---------------
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=========== ========== ========== =============== ===============
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BUS TYPE START LAST DESCRIPTION NOTES
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=========== ========== ========== =============== ===============
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Data 0x3f400000 0x3f7fffff External Flash Read
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Data 0x3f800000 0x3fbfffff External SRAM Read and Write
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=========== ========== ========== =============== ===============
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Boundary Address (External)
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---------------------------
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Instruction 0x400c2000 0x40bfffff 11512 KB External Flash Read
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Linker Segments
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---------------
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+---------------------+------------+------------+------+------------------------------+
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| DESCRIPTION | START | END | ATTR | LINKER SEGMENT NAME |
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+=====================+============+============+======+==============================+
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| FLASH mapped data: | 0x3f400010 | 0x3fc00010 | R | drom0_0_seg |
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| - .rodata | | | | |
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| - Constructors | | | | |
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| /destructors | | | | |
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+---------------------+------------+------------+------+------------------------------+
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| COMMON data RAM: | 0x3ffb0000 | 0x40000000 | RW | dram0_0_seg (NOTE 1,2,3) |
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| - .bss/.data | | | | |
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+---------------------+------------+------------+------+------------------------------+
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| IRAM for PRO cpu: | 0x40080000 | 0x400a0000 | RX | iram0_0_seg |
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| - Interrupt Vectors| | | | |
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| - Low level | | | | |
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| handlers | | | | |
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| - Xtensa/Espressif | | | | |
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| libraries | | | | |
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+---------------------+------------+------------+------+------------------------------+
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| RTC fast memory: | 0x400c0000 | 0x400c2000 | RWX | rtc_iram_seg (PRO_CPU only) |
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| - .rtc.text | | | | |
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| (unused?) | | | | |
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+---------------------+------------+------------+------+------------------------------+
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| FLASH: | 0x400d0018 | 0x40400018 | RX | iram0_2_seg (actually FLASH)|
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| - .text | | | | |
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+---------------------+------------+------------+------+------------------------------+
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| RTC slow memory: | 0x50000000 | 0x50001000 | RW | rtc_slow_seg (NOTE 4) |
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| - .rtc.data/rodata | | | | |
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| (unused?) | | | | |
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+---------------------+------------+------------+------+------------------------------+
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.. note::
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(1) Linker script will reserve space at the beginning of the segment
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for BT and at the end for trace memory.
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(2) Heap ends at the top of dram_0_seg.
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(3) Parts of this region is reserved for the ROM bootloader.
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(4) Linker script will reserve space at the beginning of the segment
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for co-processor reserve memory and at the end for ULP coprocessor
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reserve memory.
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64-bit Timers
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=============
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ESP32 has 4 generic timers of 64 bits (2 from Group 0 and 2 from Group 1). They're
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accessible as character drivers, the configuration along with a guidance on how
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to run the example and the description of the application level interface
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can be found :doc:`here </components/drivers/character/timer>`.
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Watchdog Timers
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===============
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ESP32 has 3 WDTs. 2 MWDTS from the Timers Module and 1 RWDT from the RTC Module
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(Currently not supported yet). They're accessible as character drivers,
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The configuration along with a guidance on how to run the example and the description
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of the application level interface can be found
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:doc:`here </components/drivers/character/watchdog>`.
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SMP
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===
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The ESP32 has 2 CPUs. Support is included for testing an SMP configuration.
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That configuration is still not yet ready for usage but can be enabled with
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the following configuration settings,
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in :menuselection:`RTOS Features --> Tasks and Scheduling`, with::
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CONFIG_SPINLOCK=y
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CONFIG_SMP=y
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CONFIG_SMP_NCPUS=2
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Debug Tip: During debug session, OpenOCD may mysteriously switch from one
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CPU to another. This behavior can be eliminated by uncommenting one of the
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following in ``scripts/esp32.cfg``::
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# Only configure the PRO CPU
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#set ESP32_ONLYCPU 1
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# Only configure the APP CPU
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#set ESP32_ONLYCPU 2
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Wi-Fi
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=====
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A standard network interface will be configured and can be initialized such as::
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nsh> ifup wlan0
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nsh> wapi psk wlan0 mypasswd 3
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nsh> wapi essid wlan0 myssid 1
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nsh> renew wlan0
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In this case a connection to AP with SSID ``myssid`` is done, using ``mypasswd`` as
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password. IP address is obtained via DHCP using ``renew`` command. You can check
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the result by running ``ifconfig`` afterwards.
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.. tip:: Boards usually expose a ``wapi`` defconfig which enables Wi-Fi
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Wi-Fi SoftAP
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============
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It is possible to use ESP32 as an Access Point (SoftAP). Actually there are some
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boards with a ``sta_softap`` which enables this support.
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If you are using this board config profile you can run these commands to be able
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to connect your smartphone or laptop to your board::
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nsh> ifup wlan1
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nsh> dhcpd_start wlan1
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nsh> wapi psk wlan0 mypasswd 1
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nsh> wapi essid wlan1 nuttxap 1
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In this case, you are creating the access point ``nuttxapp`` in your board and to
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connect to it on your smartphone you will be required to type the password ``mypasswd``.
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The ``dhcpd_start`` is necessary to let your board to associate an IP to your smartphone.
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Bluetooth
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=========
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These are the steps to test Bluetooth Low Energy (BLE) scan on ESP32 (i.e. Devkit board).
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First configure to use the BLE board profile::
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$ make distclean
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$ ./tools/configure.sh esp32-devkitc:ble
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$ make flash ESPTOOL_PORT=/dev/ttyUSB0
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Enter in the NSH shell using your prefered serial console tool and run the scan command::
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NuttShell (NSH) NuttX-10.2.0
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nsh> ifconfig
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bnep0 Link encap:UNSPEC at DOWN
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inet addr:0.0.0.0 DRaddr:0.0.0.0 Mask:0.0.0.0
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wlan0 Link encap:Ethernet HWaddr ac:67:b2:53:8b:ec at UP
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inet addr:10.0.0.2 DRaddr:10.0.0.1 Mask:255.255.255.0
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nsh> bt bnep0 scan start
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nsh> bt bnep0 scan stop
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nsh> bt bnep0 scan get
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Scan result:
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1. addr: 63:14:2f:b9:9f:83 type: 1
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rssi: -90
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response type: 3
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advertiser data: 1e ff 06 00 01 09 20 02 7c 33 a3 a7 cd c9 44 5b
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2. addr: 52:ca:05:b5:ad:77 type: 1
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rssi: -82
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response type: 3
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advertiser data: 1e ff 06 00 01 09 20 02 03 d1 21 57 bf 19 b3 7a
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3. addr: 46:8e:b2:cd:94:27 type: 1
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rssi: -92
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response type: 2
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advertiser data: 02 01 1a 09 ff c4 00 10 33 14 12 16 80 02 0a d4
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4. addr: 46:8e:b2:cd:94:27 type: 1
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rssi: -92
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response type: 4
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advertiser data: 18 09 5b 4c 47 5d 20 77 65 62 4f 53 20 54 56 20
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5. addr: 63:14:2f:b9:9f:83 type: 1
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rssi: -80
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response type: 3
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advertiser data: 1e ff 06 00 01 09 20 02 7c 33 a3 a7 cd c9 44 5b
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nsh>
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Using QEMU
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==========
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First follow the instructions `here <https://github.com/espressif/qemu/wiki>`_ to build QEMU.
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Enable the ``ESP32_QEMU_IMAGE`` config found in :menuselection:`Board Selection --> ESP32 binary image for QEMU`.
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Download the bootloader and the partition table from https://github.com/espressif/esp-nuttx-bootloader/releases
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and place them in a directory, say ``../esp-bins``.
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Build and generate the QEMU image::
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$ make ESPTOOL_BINDIR=../esp-bins
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A QEMU-compatible ``nuttx.merged.bin`` binary image will be created. It can be run as::
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$ qemu-system-xtensa -nographic -machine esp32 -drive file=nuttx.merged.bin,if=mtd,format=raw
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Things to Do
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============
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1. Lazy co-processor save logic supported by Xtensa. That logic works like this:
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a. CPENABLE is set to zero on each context switch, disabling all co-
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processors.
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b. If/when the task attempts to use the disabled co-processor, an
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exception occurs
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c. The co-processor exception handler re-enables the co-processor.
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Instead, the NuttX logic saves and restores CPENABLE on each context
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switch. This has disadvantages in that (1) co-processor context will
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be saved and restored even if the co-processor was never used, and (2)
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tasks must explicitly enable and disable co-processors.
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2. Currently the Xtensa port copies register state save information from
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the stack into the TCB. A more efficient alternative would be to just
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save a pointer to a register state save area in the TCB. This would
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add some complexity to signal handling and also to up_initialstate().
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But the performance improvement might be worth the effort.
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3. See SMP-related issues above
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Supported Boards
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================
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.. toctree::
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:glob:
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:maxdepth: 1
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boards/*/*
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