b984752aec
* arch: x86_64: Pour-in the x86_64 code from cRTOS repository, excluding modifications of NuttX kernel, jailhouse support and linux compatibility layer * arch: x86_64: Refactor x86_64 loading procedure for better comprehension and included support for multiboot2 * arch: x86_64: Locate the kernel at 4GB~ and modify the page table initializing procedure accordingly * arch: x86_64: Implemented kconfig option for various x86_64 capabilities, dynamic probe and check capability on lowsetup before enabling * arch: x86_64: inte64_check_capability: Use Marco to prettify the capability checking procedure * arch: x86_64: intel64_timerisr.c: Refactor with new frequency calibrating method * arch: x86_64: Fix C alias of page table and GDT/IST * arch: x86_64: Reload GTDR with GDT in high address in up_lowsetup * arch: x86_64: Consolidate MSR definition in arch/arch.h * arch: x86_64: Edit the way of handling GDT/IST in C into structures * arch: x86_64: Correct the starting point of isr/irq stack * arch: x86_64: Update up_initialize.c with the new initializing procedure * arch: x86_64: up_map_region now take flags instead of assuming WR/PRESENT * arch: x86_64: Overhual of interrupt initialization procedure * arch: x86_64: Properly configure the heap to be memory as [_ebss, end of memory] * arch: x86_64: Try to probe the TSC frequency, fall-back to user specified frequency on failure * arch: x86_64: Remove debug printing during restore_aux, causing infinite CTX bug * arch: x86_64: for X86 16500 serial interrupt to work, OUT2 of MCR must be 1. Make it stuck at 1 after boot * arch: x86_64: Correctly apply license header, comment and format code * arch: x86_64: properly send a SIGFPE on floating point error * arch: x86_64: Remove unused variable in up_restore_auxstate * arch: x86_64: properly trash the processor with an infinite loop * arch: x86_64: Fix typo in ISR handler causing ISR not handled * arch: x86_64: Fix possibile race conditions with scheduler debug option on in signal handling path * arch: x86_64: Fix typo in MSR_X2APIC_LVTT_TSC_DEADLINE * arch: x86_64: Migrate tickless implementation to the new MSR naming and frequency calibration method * board: x86_64: qemu: Add guard to exclude up_netinitialize when compiling without net support * arch: x86_64: update defconfigs * arch: x86_64: rename qemu as qemu-intel64 * arch: x86_64: update Board readme
207 lines
4.8 KiB
C
207 lines
4.8 KiB
C
/****************************************************************************
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* arch/x86_64/include/intel64/io.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly
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* through arch/io.h
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*/
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#ifndef __ARCH_X86_64_INCLUDE_INTEL64_IO_H
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#define __ARCH_X86_64_INCLUDE_INTEL64_IO_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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#include <arch/arch.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/* Standard x86 Port I/O */
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static inline void outb(uint8_t regval, uint16_t port)
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{
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asm volatile(
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"\toutb %0,%1\n"
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:
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: "a" (regval), "dN" (port)
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);
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}
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static inline uint8_t inb(uint16_t port)
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{
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uint8_t regval;
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asm volatile(
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"\tinb %1,%0\n"
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: "=a" (regval)
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: "dN" (port)
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);
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return regval;
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}
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static inline void outw(uint16_t regval, uint16_t port)
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{
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asm volatile(
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"\toutw %0,%1\n"
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:
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: "a" (regval), "dN" (port)
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);
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}
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static inline uint16_t inw(uint16_t port)
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{
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uint16_t regval;
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asm volatile(
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"\tinw %1,%0\n"
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: "=a" (regval)
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: "dN" (port)
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);
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return regval;
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}
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static inline void outl(uint32_t regval, uint16_t port)
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{
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asm volatile(
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"\toutl %0,%1\n"
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:
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: "a" (regval), "dN" (port)
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);
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}
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static inline uint32_t inl(uint16_t port)
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{
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uint32_t regval;
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asm volatile(
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"\tinl %1,%0\n"
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: "=a" (regval)
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: "dN" (port)
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);
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return regval;
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}
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/* MMIO */
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static inline uint8_t mmio_read8(void *address)
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{
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return *(volatile uint8_t *)address;
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}
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static inline uint16_t mmio_read16(void *address)
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{
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return *(volatile uint16_t *)address;
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}
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static inline uint32_t mmio_read32(void *address)
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{
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uint32_t value;
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/* Assembly-encoded to match the hypervisor MMIO parser support */
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asm volatile("movl (%1),%0" : "=r" (value) : "r" (address));
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return value;
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}
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static inline uint64_t mmio_read64(void *address)
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{
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return *(volatile uint64_t *)address;
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}
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static inline void mmio_write8(void *address, uint8_t value)
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{
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*(volatile uint8_t *)address = value;
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}
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static inline void mmio_write16(void *address, uint16_t value)
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{
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*(volatile uint16_t *)address = value;
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}
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static inline void mmio_write32(void *address, uint32_t value)
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{
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/* Assembly-encoded to match the hypervisor MMIO parser support */
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asm volatile("movl %0,(%1)" : : "r" (value), "r" (address));
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}
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static inline void mmio_write64(void *address, uint64_t value)
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{
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*(volatile uint64_t *)address = value;
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}
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static inline void up_trash_cpu(void)
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{
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for (; ; )
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{
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asm volatile ("cli;hlt;");
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}
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asm("ud2":::"memory");
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}
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static inline void up_invalid_TLB(uintptr_t start, uintptr_t end)
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{
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uintptr_t i;
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start = start & PAGE_MASK;
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end = (end + PAGE_SIZE - 1) & PAGE_MASK;
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for (i = start; i < end; i += PAGE_SIZE)
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{
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asm("invlpg %0;":: "m"(i):"memory");
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}
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}
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_X86_64_INCLUDE_INTEL64_IO_H */
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