114 lines
5.5 KiB
Plaintext
114 lines
5.5 KiB
Plaintext
/****************************************************************************
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* boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and
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* 192Kb of SRAM. SRAM is split up into three blocks:
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*
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* 1) 112KB of SRAM beginning at address 0x2000:0000
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* 2) 16KB of SRAM beginning at address 0x2001:c000
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* 3) 64KB of CCM SRAM beginning at address 0x1000:0000
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*
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* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
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* where the code expects to begin execution by jumping to the entry point in
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* the 0x0800:0000 address range.
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*
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* For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
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* FLASH and 8Kb of SRAM. (See boards/stm32f4discovery/scripts/kernel-space.ld).
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* Allowing additional memory permitis configuring debug instrumentation to
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* be added to the kernel space without overflowing the partition. This could
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* just as easily be set to 256Kb or even 512Kb.
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*
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* Alignment of the user space FLASH partition is also a critical factor:
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* The user space FLASH partition will be spanned with a single region of
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* size 2**n bytes. The alignment of the user-space region must be the same.
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* As a consequence, as the user-space increases in size, the alignment
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* requirement also increases.
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*
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* This alignment requirement means that the largest user space FLASH region
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* you can have will be 512KB at it would have to be positioned at
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* 0x08800000 (it cannot be positioned at 0x0800000 because vectors power-up
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* reset vectors are places at the beginning of that range). If you change
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* this address, don't forget to change the CONFIG_NUTTX_USERSPACE
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* configuration setting to match and to modify the check in kernel/userspace.c.
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*
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* With 112Kb of SRAM a 64Kb user heap would seem possible but it is not in
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* the current organization of SRAM memory (that could be changed with a
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* little effort). The current ordering of SRAM is: (1) kernel .bss/.data,
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* (2) user .bss/.data, (3) kernel heap (determined by CONFIG_MM_KERNEL_HEAPSIZE),
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* and (4) the user heap. The maximum size of the user space heap is then
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* limited to 32Kb beginning at address 0x20008000.
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*
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* Both of these alignment limitations could be reduced by using multiple
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* regions to map the FLASH/SDRAM range or perhaps with some clever use of
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* subregions or with multiple MPU regions per memory region.
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*
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* NOTE: The MPU is used in a mode where mappings are not required for
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* kernel addresses and, hence, there are not alignment issues for those
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* case. Only the user address spaces suffer from alignment requirements.
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* However, in order to exploit this fact, we would still need to change
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* the ordering of memory regions in SRAM.
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*
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* A detailed memory map for the 112KB SRAM region is as follows:
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*
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* 0x2000 0000: Kernel .data region. Typical size: 0.1KB
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* ------ ---- Kernel .bss region. Typical size: 1.8KB
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* 0x2000 0800: Kernel IDLE thread stack (approximate). Size is
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* determined by CONFIG_IDLETHREAD_STACKSIZE and
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* adjustments for alignment. Typical is 1KB.
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* ------ ---- Padded to 8KB
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* 0x2000 2000: User .data region. Size is variable.
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* ------ ---- User .bss region Size is variable.
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* 0x2000 4000: Beginning of kernel heap. Size determined by
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* CONFIG_MM_KERNEL_HEAPSIZE which must be set to 16Kb.
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* 0x2000 8000: Beginning of 32Kb user heap.
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* 0x2001 0000: The remainder of SRAM is, unfortunately, wasted.
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* 0x2001 c000: End+1 of CPU RAM
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*/
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MEMORY
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{
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/* 1024Kb FLASH */
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kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
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uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K
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xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K
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/* 112Kb of contiguous SRAM */
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ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
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usram (rwx) : ORIGIN = 0x20002000, LENGTH = 8K
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xsram (rwx) : ORIGIN = 0x20008000, LENGTH = 96K
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}
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