748 lines
22 KiB
C
748 lines
22 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32f10xxx_dma.c
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*
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* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <debug.h>
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#include <errno.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "os_internal.h"
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#include "chip.h"
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#include "stm32_dma.h"
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#include "stm32.h"
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/* Only for the STM32F10xx family for now */
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define DMA1_NCHANNELS 7
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#if STM32_NDMA > 1
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# define DMA2_NCHANNELS 5
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# define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS)
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#else
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# define DMA_NCHANNELS DMA1_NCHANNELS
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#endif
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#ifndef CONFIG_DMA_PRI
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# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
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#endif
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/* Convert the DMA channel base address to the DMA register block address */
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#define DMA_BASE(ch) (ch & 0xfffffc00)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure descibes one DMA channel */
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struct stm32_dma_s
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{
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uint8_t chan; /* DMA channel number (0-6) */
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uint8_t irq; /* DMA channel IRQ number */
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sem_t sem; /* Used to wait for DMA channel to become available */
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uint32_t base; /* DMA register channel base address */
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dma_callback_t callback; /* Callback invoked when the DMA completes */
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void *arg; /* Argument passed to callback function */
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* This array describes the state of each DMA */
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static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
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{
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{
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.chan = 0,
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.irq = STM32_IRQ_DMA1CH1,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
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},
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{
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.chan = 1,
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.irq = STM32_IRQ_DMA1CH2,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
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},
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{
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.chan = 2,
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.irq = STM32_IRQ_DMA1CH3,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
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},
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{
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.chan = 3,
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.irq = STM32_IRQ_DMA1CH4,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
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},
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{
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.chan = 4,
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.irq = STM32_IRQ_DMA1CH5,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
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},
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{
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.chan = 5,
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.irq = STM32_IRQ_DMA1CH6,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
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},
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{
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.chan = 6,
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.irq = STM32_IRQ_DMA1CH7,
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.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
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},
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#if STM32_NDMA > 1
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{
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.chan = 0,
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.irq = STM32_IRQ_DMA2CH1,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0),
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},
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{
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.chan = 1,
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.irq = STM32_IRQ_DMA2CH2,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1),
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},
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{
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.chan = 2,
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.irq = STM32_IRQ_DMA2CH3,
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2),
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},
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{
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.chan = 3,
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#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
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.irq = STM32_IRQ_DMA2CH4,
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#else
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.irq = STM32_IRQ_DMA2CH45,
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#endif
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
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},
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{
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.chan = 4,
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#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
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.irq = STM32_IRQ_DMA2CH5,
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#else
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.irq = STM32_IRQ_DMA2CH45,
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#endif
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.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4),
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},
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* DMA register access functions
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****************************************************************************/
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/* Get non-channel register from DMA1 or DMA2 */
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static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, uint32_t offset)
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{
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return getreg32(DMA_BASE(dmach->base) + offset);
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}
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/* Write to non-channel register in DMA1 or DMA2 */
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static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value)
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{
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putreg32(value, DMA_BASE(dmach->base) + offset);
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}
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/* Get channel register from DMA1 or DMA2 */
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static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, uint32_t offset)
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{
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return getreg32(dmach->base + offset);
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}
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/* Write to channel register in DMA1 or DMA2 */
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static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value)
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{
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putreg32(value, dmach->base + offset);
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}
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/************************************************************************************
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* Name: stm32_dmatake() and stm32_dmagive()
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*
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* Description:
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* Used to get exclusive access to a DMA channel.
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*
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************************************************************************************/
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static void stm32_dmatake(FAR struct stm32_dma_s *dmach)
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{
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/* Take the semaphore (perhaps waiting) */
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while (sem_wait(&dmach->sem) != 0)
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{
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/* The only case that an error should occur here is if the wait was awakened
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* by a signal.
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*/
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ASSERT(errno == EINTR);
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}
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}
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static inline void stm32_dmagive(FAR struct stm32_dma_s *dmach)
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{
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(void)sem_post(&dmach->sem);
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}
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/************************************************************************************
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* Name: stm32_dmachandisable
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*
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* Description:
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* Disable the DMA channel
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*
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************************************************************************************/
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static void stm32_dmachandisable(struct stm32_dma_s *dmach)
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{
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uint32_t regval;
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/* Disable all interrupts at the DMA controller */
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regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
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regval &= ~DMA_CCR_ALLINTS;
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/* Disable the DMA channel */
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regval &= ~DMA_CCR_EN;
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dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
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/* Clear pending channel interrupts */
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dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmach->chan));
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}
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/************************************************************************************
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* Name: stm32_dmainterrupt
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*
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* Description:
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* DMA interrupt handler
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*
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************************************************************************************/
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static int stm32_dmainterrupt(int irq, void *context)
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{
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struct stm32_dma_s *dmach;
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uint32_t isr;
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int chndx = 0;
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/* Get the channel structure from the interrupt number */
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if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7)
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{
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chndx = irq - STM32_IRQ_DMA1CH1;
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}
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else
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#if STM32_NDMA > 1
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#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
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if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
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#else
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if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
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#endif
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{
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chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
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}
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else
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#endif
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{
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PANIC();
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}
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dmach = &g_dma[chndx];
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/* Get the interrupt status (for this channel only) */
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isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan);
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/* Clear the interrupts we are handling */
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dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr);
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/* Invoke the callback */
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if (dmach->callback)
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{
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dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), dmach->arg);
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}
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_dmainitialize
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*
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* Description:
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* Initialize the DMA subsystem
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void weak_function up_dmainitialize(void)
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{
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struct stm32_dma_s *dmach;
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int chndx;
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/* Initialize each DMA channel */
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for (chndx = 0; chndx < DMA_NCHANNELS; chndx++)
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{
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dmach = &g_dma[chndx];
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sem_init(&dmach->sem, 0, 1);
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/* Attach DMA interrupt vectors */
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(void)irq_attach(dmach->irq, stm32_dmainterrupt);
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/* Disable the DMA channel */
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stm32_dmachandisable(dmach);
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/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
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up_enable_irq(dmach->irq);
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/* Set the interrrupt priority */
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up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI);
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}
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}
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/****************************************************************************
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* Name: stm32_dmachannel
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*
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* Description:
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* Allocate a DMA channel. This function gives the caller mutually
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* exclusive access to the DMA channel specified by the 'chndx' argument.
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* DMA channels are shared on the STM32: Devices sharing the same DMA
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* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
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* stm32_dma.h.
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*
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* If the DMA channel is not available, then stm32_dmachannel() will wait
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* until the holder of the channel relinquishes the channel by calling
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* stm32_dmafree(). WARNING: If you have two devices sharing a DMA
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* channel and the code never releases the channel, the stm32_dmachannel
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* call for the other will hang forever in this function! Don't let your
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* design do that!
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*
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* Hmm.. I suppose this interface could be extended to make a non-blocking
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* version. Feel free to do that if that is what you need.
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*
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* Input parameter:
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* chndx - Identifies the stream/channel resource. For the STM32 F1, this
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* is simply the channel number as provided by the DMACHAN_* definitions
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* in chip/stm32f10xxx_dma.h.
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*
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* Returned Value:
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* Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL,
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* void* DMA channel handle. (If 'chndx' is invalid, the function will
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* assert if debug is enabled or do something ignorant otherwise).
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*
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* Assumptions:
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* - The caller does not hold he DMA channel.
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* - The caller can wait for the DMA channel to be freed if it is no
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* available.
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*
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****************************************************************************/
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DMA_HANDLE stm32_dmachannel(unsigned int chndx)
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{
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struct stm32_dma_s *dmach = &g_dma[chndx];
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DEBUGASSERT(chndx < DMA_NCHANNELS);
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/* Get exclusive access to the DMA channel -- OR wait until the channel
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* is available if it is currently being used by another driver
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*/
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stm32_dmatake(dmach);
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/* The caller now has exclusive use of the DMA channel */
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return (DMA_HANDLE)dmach;
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}
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/****************************************************************************
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* Name: stm32_dmafree
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*
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* Description:
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* Release a DMA channel. If another thread is waiting for this DMA channel
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* in a call to stm32_dmachannel, then this function will re-assign the
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* DMA channel to that thread and wake it up. NOTE: The 'handle' used
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* in this argument must NEVER be used again until stm32_dmachannel() is
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* called again to re-gain access to the channel.
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* - The caller holds the DMA channel.
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* - There is no DMA in progress
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*
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****************************************************************************/
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void stm32_dmafree(DMA_HANDLE handle)
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{
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struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
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DEBUGASSERT(handle != NULL);
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/* Release the channel */
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stm32_dmagive(dmach);
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}
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/****************************************************************************
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* Name: stm32_dmasetup
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*
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* Description:
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* Configure DMA before using
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*
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****************************************************************************/
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void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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size_t ntransfers, uint32_t ccr)
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{
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struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
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uint32_t regval;
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/* Then DMA_CNDTRx register can only be modified if the DMA channel is
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* disabled.
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*/
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regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
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regval &= ~(DMA_CCR_EN);
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dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
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/* Set the peripheral register address in the DMA_CPARx register. The data
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* will be moved from/to this address to/from the memory after the
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* peripheral event.
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*/
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dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr);
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/* Set the memory address in the DMA_CMARx register. The data will be
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* written to or read from this memory after the peripheral event.
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*/
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dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr);
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/* Configure the total number of data to be transferred in the DMA_CNDTRx
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* register. After each peripheral event, this value will be decremented.
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*/
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dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers);
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|
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/* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx
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* register. Configure data transfer direction, circular mode, peripheral & memory
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* incremented mode, peripheral & memory data size, and interrupt after
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* half and/or full transfer in the DMA_CCRx register.
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*/
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regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
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regval &= ~(DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
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DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
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ccr &= (DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
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DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
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regval |= ccr;
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dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
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}
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|
|
/****************************************************************************
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|
* Name: stm32_dmastart
|
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*
|
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* Description:
|
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* Start the DMA transfer
|
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*
|
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* Assumptions:
|
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* - DMA handle allocated by stm32_dmachannel()
|
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* - No DMA in progress
|
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*
|
|
****************************************************************************/
|
|
|
|
void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback,
|
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void *arg, bool half)
|
|
{
|
|
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
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uint32_t ccr;
|
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|
|
DEBUGASSERT(handle != NULL);
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|
|
/* Save the callback info. This will be invoked whent the DMA commpletes */
|
|
|
|
dmach->callback = callback;
|
|
dmach->arg = arg;
|
|
|
|
/* Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
|
|
* As soon as the channel is enabled, it can serve any DMA request from the
|
|
* peripheral connected on the channel.
|
|
*/
|
|
|
|
ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
|
ccr |= DMA_CCR_EN;
|
|
|
|
/* In normal mode, interrupt at either half or full completion. In circular mode,
|
|
* always interrupt on buffer wrap, and optionally interrupt at the halfway point.
|
|
*/
|
|
|
|
if ((ccr & DMA_CCR_CIRC) == 0)
|
|
{
|
|
/* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
|
|
* set and an interrupt is generated if the Half-Transfer Interrupt Enable
|
|
* bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
|
|
* (TCIF) is set and an interrupt is generated if the Transfer Complete
|
|
* Interrupt Enable bit (TCIE) is set.
|
|
*/
|
|
|
|
ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE));
|
|
}
|
|
else
|
|
{
|
|
/* In nonstop mode, when the transfer completes it immediately resets
|
|
* and starts again. The transfer-complete interrupt is thus always
|
|
* enabled, and the half-complete interrupt can be used in circular
|
|
* mode to determine when the buffer is half-full, or in double-buffered
|
|
* mode to determine when one of the two buffers is full.
|
|
*/
|
|
|
|
ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE;
|
|
}
|
|
|
|
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmastop
|
|
*
|
|
* Description:
|
|
* Cancel the DMA. After stm32_dmastop() is called, the DMA channel is
|
|
* reset and stm32_dmasetup() must be called before stm32_dmastart() can be
|
|
* called again
|
|
*
|
|
* Assumptions:
|
|
* - DMA handle allocated by stm32_dmachannel()
|
|
*
|
|
****************************************************************************/
|
|
|
|
void stm32_dmastop(DMA_HANDLE handle)
|
|
{
|
|
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
|
stm32_dmachandisable(dmach);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmaresidual
|
|
*
|
|
* Description:
|
|
* Returns the number of bytes remaining to be transferred
|
|
*
|
|
* Assumptions:
|
|
* - DMA handle allocated by stm32_dmachannel()
|
|
*
|
|
****************************************************************************/
|
|
|
|
size_t stm32_dmaresidual(DMA_HANDLE handle)
|
|
{
|
|
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
|
|
|
return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmacapable
|
|
*
|
|
* Description:
|
|
* Check if the DMA controller can transfer data to/from given memory
|
|
* address. This depends on the internal connections in the ARM bus matrix
|
|
* of the processor. Note that this only applies to memory addresses, it
|
|
* will return false for any peripheral address.
|
|
*
|
|
* Returned value:
|
|
* True, if transfer is possible.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_STM32_DMACAPABLE
|
|
bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
|
|
{
|
|
uint32_t transfer_size;
|
|
uint32_t mend;
|
|
|
|
/* Verify that the address conforms to the memory transfer size.
|
|
* Transfers to/from memory performed by the DMA controller are
|
|
* required to be aligned to their size.
|
|
*
|
|
* See ST RM0090 rev4, section 9.3.11
|
|
*
|
|
* Compute mend inline to avoid a possible non-constant integer
|
|
* multiply.
|
|
*/
|
|
|
|
switch (ccr & STM32_DMA_SCR_MSIZE_MASK)
|
|
{
|
|
case DMA_SCR_MSIZE_8BITS:
|
|
transfer_size = 1;
|
|
mend = maddr + count - 1;
|
|
break;
|
|
|
|
case DMA_SCR_MSIZE_16BITS:
|
|
transfer_size = 2;
|
|
mend = maddr + (count << 1) - 1;
|
|
break;
|
|
|
|
case DMA_SCR_MSIZE_32BITS:
|
|
transfer_size = 4;
|
|
mend = maddr + (count << 2) - 1;
|
|
break;
|
|
|
|
default
|
|
return false;
|
|
}
|
|
|
|
if ((maddr & (transfer_size - 1)) != 0)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
/* Verify that the transfer is to a memory region that supports DMA. */
|
|
|
|
if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK))
|
|
{
|
|
return false;
|
|
}
|
|
|
|
switch (maddr & STM32_REGION_MASK)
|
|
{
|
|
#if defined(CONFIG_STM32_STM32F10XX)
|
|
case STM32_FSMC_BANK1:
|
|
case STM32_FSMC_BANK2:
|
|
case STM32_FSMC_BANK3:
|
|
case STM32_FSMC_BANK4:
|
|
#endif
|
|
case STM32_SRAM_BASE:
|
|
case STM32_CODE_BASE:
|
|
/* All RAM and flash is supported */
|
|
|
|
return true;
|
|
|
|
default:
|
|
/* Everything else is unsupported by DMA */
|
|
|
|
return false;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmasample
|
|
*
|
|
* Description:
|
|
* Sample DMA register contents
|
|
*
|
|
* Assumptions:
|
|
* - DMA handle allocated by stm32_dmachannel()
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_DEBUG_DMA
|
|
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
|
|
{
|
|
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
|
irqstate_t flags;
|
|
|
|
flags = irqsave();
|
|
regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET);
|
|
regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
|
regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET);
|
|
regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET);
|
|
regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET);
|
|
irqrestore(flags);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmadump
|
|
*
|
|
* Description:
|
|
* Dump previously sampled DMA register contents
|
|
*
|
|
* Assumptions:
|
|
* - DMA handle allocated by stm32_dmachannel()
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_DEBUG_DMA
|
|
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
|
|
const char *msg)
|
|
{
|
|
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
|
uint32_t dmabase = DMA_BASE(dmach->base);
|
|
|
|
dmadbg("DMA Registers: %s\n", msg);
|
|
dmadbg(" ISRC[%08x]: %08x\n", dmabase + STM32_DMA_ISR_OFFSET, regs->isr);
|
|
dmadbg(" CCR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr);
|
|
dmadbg(" CNDTR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr);
|
|
dmadbg(" CPAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar);
|
|
dmadbg(" CMAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar);
|
|
}
|
|
#endif
|
|
|
|
#endif /* CONFIG_STM32_STM32F10XX */
|