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gnu
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This commit changes the lazy and non-lazy exception handler to remove a couple of cpsid instructions from them on ARMv7-m. If my understanding is correct then these interrupt manipulations aren't doing anything anyway because prioritization stops secondary interrupts arriving and, even if they did work, they would have introduced race conditions for the period of time between the interrupt arriving and further interrupts being disabled.
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2018-12-06 07:20:21 -06:00 |
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iar
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arch/arm/src/stm32l4: STM32L4 has fetchadd and testset
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2018-06-18 07:14:52 -06:00 |
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arch_clean_dcache_all.c
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arch_clean_dcache.c
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arch/: Remove dangling space at the end of lines.
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2017-06-28 13:16:48 -06:00 |
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arch_disable_dcache.c
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arch_enable_dcache.c
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arch_flush_dcache_all.c
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arch_flush_dcache.c
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arch/: Remove dangling space at the end of lines.
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2017-06-28 13:16:48 -06:00 |
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arch_invalidate_dcache_all.c
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arch_invalidate_dcache.c
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This commit adds a new function arch_invalidate_dcache_by_addr(). It takes the same parameters as arch_invalidate_dcache(), but performs invalidation of only the lines in cache that need to be invalidated. This new function could be used as a a direct replacement for arch_invalidate_dcache().
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2018-11-20 14:03:42 -06:00 |
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cache.h
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This commit adds a new function arch_invalidate_dcache_by_addr(). It takes the same parameters as arch_invalidate_dcache(), but performs invalidation of only the lines in cache that need to be invalidated. This new function could be used as a a direct replacement for arch_invalidate_dcache().
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2018-11-20 14:03:42 -06:00 |
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dwt.h
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arch/arm/src/armv7-m: Make naming used in ARM register definition files a little more compatible with naming used in other header files.
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2018-11-27 10:36:40 -06:00 |
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etm.h
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exc_return.h
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Squashed commit of the following:
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2018-06-20 12:30:37 -06:00 |
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fpb.h
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arch/arm/include/tiva: Add support for cc13xx interrupts. arch/arm/src/armv7-m: Add FPB header file.
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2018-12-03 07:26:02 -06:00 |
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itm_syslog.h
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itm.h
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arch/arm/src/armv7-m/itm.h: Fix missing space causing macro issues
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2018-12-01 06:12:29 -06:00 |
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Kconfig
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Kconfig files, binfmt/libelf, libs/libc/machin, libs/libxx: Correct libcxx exception handling by introducing the generic config(CXX_EXCEPTION and CXX_LIBSUPCXX)
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2019-01-26 11:23:31 -06:00 |
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mpu.h
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Revert "arch/arm/armv7-m: MPU: mpu_log2regionceil needs take into account the offset too"
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2019-01-08 07:46:19 -06:00 |
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nvic.h
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This commit adds a new function arch_invalidate_dcache_by_addr(). It takes the same parameters as arch_invalidate_dcache(), but performs invalidation of only the lines in cache that need to be invalidated. This new function could be used as a a direct replacement for arch_invalidate_dcache().
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2018-11-20 14:03:42 -06:00 |
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psr.h
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ram_vectors.h
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arch/arm: Fix an error found in build testing.
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2018-06-20 13:12:54 -06:00 |
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svcall.h
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systick.h
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arch/arm/src/armv7-m: Implement SYSTICK timer driver
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2018-08-23 10:09:56 -06:00 |
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Toolchain.defs
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Add CLANG definitions in Kconfig and Toolchain.defs
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2017-07-02 06:42:48 -06:00 |
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tpi.h
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arch/arm/src/armv7-m: Make naming used in ARM register definition files a little more compatible with naming used in other header files.
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2018-11-27 10:36:40 -06:00 |
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up_assert.c
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arch/xxx/src/xxx/up_assert.c: Dump CPU0 IDLE stack only when PID equals 0. IDLE threads of other CPUs do not need this special check
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2019-01-26 10:59:23 -06:00 |
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up_blocktask.c
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Replace all ASSERT with DEBUGASSERT to save the code space
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2018-08-24 06:58:30 -06:00 |
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up_coherent_dcache.c
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Remove comment blocks from empty file sections.
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2017-01-19 11:59:41 -06:00 |
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up_copyarmstate.c
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Squashed commit of the following:
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2018-06-20 12:30:37 -06:00 |
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up_copyfullstate.c
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Remove comment blocks from empty file sections.
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2017-01-19 11:59:41 -06:00 |
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up_doirq.c
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Remove uninterpretable comment.
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2017-01-26 07:20:35 -06:00 |
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up_hardfault.c
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arch/arm/src: Remove general register dump from fault handler since the same info already dump in PANIC
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2018-11-11 12:47:03 -06:00 |
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up_initialstate.c
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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up_itm_syslog.c
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arch/arm/src/armv7-m: Make naming used in ARM register definition files a little more compatible with naming used in other header files.
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2018-11-27 10:36:40 -06:00 |
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up_itm.c
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arch/arm/src/armv7-m: Make naming used in ARM register definition files a little more compatible with naming used in other header files.
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2018-11-27 10:36:40 -06:00 |
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up_memfault.c
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arch/arm/src: Remove general register dump from fault handler since the same info already dump in PANIC
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2018-11-11 12:47:03 -06:00 |
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up_mpu.c
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Revert "arch/arm/armv7-m: MPU: mpu_log2regionceil needs take into account the offset too"
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2019-01-08 07:46:19 -06:00 |
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up_ramvec_attach.c
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arch/arm: Fix an error found in build testing.
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2018-06-20 13:12:54 -06:00 |
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up_ramvec_initialize.c
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Remove comment blocks from empty file sections.
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2017-01-19 11:59:41 -06:00 |
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up_releasepending.c
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Revert "All CMP platforms: Apply same fix verified on other platforms found on Xtensa."
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2016-12-25 07:08:44 -06:00 |
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up_reprioritizertr.c
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Replace non critical PANIC with DEBUGPANIC to save the code space
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2018-08-24 06:21:15 -06:00 |
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up_schedulesigaction.c
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In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
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2018-12-03 17:41:59 -06:00 |
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up_sigdeliver.c
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arch/: Fix an interlock that was broken by commit 641a98a434 in all implementations of up_sigdeliver.
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2019-02-03 17:14:32 -06:00 |
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up_signal_dispatch.c
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Trivial changes from review of last PR.
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2018-02-14 08:20:40 -06:00 |
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up_stackcheck.c
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up_svcall.c
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arm syscalls: svcall/sycall logic needs to get the ucontext argument from R4 instead of stack since all syscall parameters pass from registers in syscall.h
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2018-08-24 07:11:18 -06:00 |
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up_systemreset.c
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up_systick.c
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arch/arm/src/armv7-m/up_systick.c: Fix warning: 'NVIC_IRQ_SYSTICK redefined'
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2018-08-29 06:10:52 -06:00 |
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up_trigger_irq.c
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arch/arm/src/armv7-m/up_trigger_irq.c: Correct copyright and authorship of file. Cloning error.
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2018-08-25 11:12:12 -06:00 |
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up_unblocktask.c
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Replace all ASSERT with DEBUGASSERT to save the code space
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2018-08-24 06:58:30 -06:00 |
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up_vectors.c
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arch/arm/src/armv6+7-m/up_vectors.c: Fix the type mismatch warning for _ebss
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2018-08-24 07:04:51 -06:00 |
