3a32937b9b
since the directory only contains only BCM43362 and BCM43438 related code.
600 lines
16 KiB
C
600 lines
16 KiB
C
/****************************************************************************
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* drivers/wireless/bcm43xxx/ieee80211/bcmf_core.c
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*
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* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
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* Author: Simon Piriou <spiriou31@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/compiler.h>
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#include <debug.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <string.h>
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#include <nuttx/arch.h>
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#include <nuttx/kmalloc.h>
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#include "bcmf_core.h"
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#include "bcmf_sdio.h"
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#include "bcmf_sdio_regs.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Agent registers (common for every core) */
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#define BCMA_IOCTL 0x0408 /* IO control */
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#define BCMA_IOST 0x0500 /* IO status */
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#define BCMA_RESET_CTL 0x0800 /* Reset control */
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#define BCMA_RESET_ST 0x0804
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#define BCMA_IOCTL_CLK 0x0001
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#define BCMA_IOCTL_FGC 0x0002
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#define BCMA_IOCTL_CORE_BITS 0x3FFC
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#define BCMA_IOCTL_PME_EN 0x4000
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#define BCMA_IOCTL_BIST_EN 0x8000
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#define BCMA_IOST_CORE_BITS 0x0FFF
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#define BCMA_IOST_DMA64 0x1000
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#define BCMA_IOST_GATED_CLK 0x2000
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#define BCMA_IOST_BIST_ERROR 0x4000
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#define BCMA_IOST_BIST_DONE 0x8000
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#define BCMA_RESET_CTL_RESET 0x0001
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/* SOCSRAM core registers */
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#define SOCSRAM_BANKX_INDEX ((uint32_t) (0x18004000 + 0x10) )
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#define SOCSRAM_BANKX_PDA ((uint32_t) (0x18004000 + 0x44) )
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/* Transfer size properties */
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#define BCMF_UPLOAD_TRANSFER_SIZE (64 * 256)
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/* Define this to validate uploaded materials */
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/* #define DBG_VALIDATE_UPLOAD */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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#ifdef DBG_VALIDATE_UPLOAD
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static uint8_t compare_buffer[BCMF_UPLOAD_TRANSFER_SIZE];
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#endif
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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static int bcmf_core_set_backplane_window(FAR struct bcmf_sdio_dev_s *sbus,
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uint32_t address);
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static int bcmf_upload_binary(FAR struct bcmf_sdio_dev_s *sbusv,
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uint32_t address, uint8_t *buf,
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unsigned int len);
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static int bcmf_upload_nvram(FAR struct bcmf_sdio_dev_s *sbus);
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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int bcmf_core_set_backplane_window(FAR struct bcmf_sdio_dev_s *sbus,
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uint32_t address)
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{
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int ret;
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int i;
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address &= ~SBSDIO_SB_OFT_ADDR_MASK;
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for (i = 1; i < 4; i++)
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{
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uint8_t addr_part = (address >> (8*i)) & 0xff;
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uint8_t cur_addr_part = (sbus->backplane_current_addr >> (8*i)) & 0xff;
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if (addr_part != cur_addr_part)
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{
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/* Update current backplane base address */
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ret = bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_SBADDRLOW + i - 1,
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addr_part);
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if (ret != OK)
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{
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return ret;
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}
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sbus->backplane_current_addr &= ~(0xff << (8*i));
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sbus->backplane_current_addr |= addr_part << (8*i);
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}
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}
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return OK;
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}
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int bcmf_upload_binary(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
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uint8_t *buf, unsigned int len)
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{
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unsigned int size;
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#ifdef DBG_VALIDATE_UPLOAD
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uint32_t validate_address = address;
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uint8_t *validate_buffer = buf;
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unsigned int validate_len = len;
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#endif
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while (len > 0)
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{
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/* Set the backplane window to include the start address */
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int ret = bcmf_core_set_backplane_window(sbus, address);
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if (ret != OK)
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{
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wlerr("Backplane setting failed at %08x\n", address);
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return ret;
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}
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if (len > BCMF_UPLOAD_TRANSFER_SIZE)
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{
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size = BCMF_UPLOAD_TRANSFER_SIZE;
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}
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else
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{
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size = len;
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}
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/* Transfer firmware data */
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ret = bcmf_transfer_bytes(sbus, true, 1,
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address & SBSDIO_SB_OFT_ADDR_MASK, buf, size);
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if (ret != OK)
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{
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wlerr("transfer failed %d %x %d\n", ret, address, size);
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return ret;
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}
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len -= size;
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address += size;
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buf += size;
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}
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#ifdef DBG_VALIDATE_UPLOAD
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wlwarn("Validating....\n");
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while (validate_len > 0)
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{
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/* Set the backplane window to include the start address */
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int ret = bcmf_core_set_backplane_window(sbus, validate_address);
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if (ret != OK)
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{
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wlerr("Backplane setting failed at %08x\n", validate_address);
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return ret;
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}
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if (validate_len > BCMF_UPLOAD_TRANSFER_SIZE)
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{
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size = BCMF_UPLOAD_TRANSFER_SIZE;
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}
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else
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{
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size = validate_len;
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}
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/* Transfer firmware data */
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ret = bcmf_transfer_bytes(sbus, false, 1,
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validate_address & SBSDIO_SB_OFT_ADDR_MASK,
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compare_buffer, size);
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if (ret != OK)
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{
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wlerr("validate transfer failed %d %x %d\n", ret, validate_address,
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size);
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return ret;
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}
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if (memcmp(validate_buffer, compare_buffer, size))
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{
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wlerr("Match failed at address base %08x\n", validate_address);
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return -EILSEQ;
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}
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validate_len -= size;
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validate_address += size;
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validate_buffer += size;
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}
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wlwarn("Validation passed\n");
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#endif
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return OK;
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}
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#ifdef CONFIG_IEEE80211_BROADCOM_FWFILES
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int bcmf_upload_file(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
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FAR const char *path)
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{
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struct file finfo;
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FAR uint8_t *buf;
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size_t total_read;
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ssize_t nread;
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int ret;
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/* Open the file in the detached state */
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ret = file_open(&finfo, path, O_RDONLY | O_BINARY);
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if (ret < 0)
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{
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wlerr("ERROR: Failed to open the FILE MTD file %s: %d\n", path, ret);
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return ret;
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}
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/* Allocate an I/O buffer */
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buf = (FAR uint8_t *)kmm_malloc(BCMF_UPLOAD_TRANSFER_SIZE);
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if (buf == NULL)
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{
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wlerr("ERROR: Failed allocate an I/O buffer\n");
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ret = -ENOMEM;
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goto errout_with_file;
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}
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/* Loop until the firmware has been loaded */
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do
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{
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/* Set the backplane window to include the start address */
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nread = file_read(&finfo, buf, BCMF_UPLOAD_TRANSFER_SIZE);
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if (nread < 0)
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{
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ret = (int)nread;
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wlerr("ERROR: Failed to read file: %d\n", ret);
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goto errout_with_buf;
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}
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if (nread == 0)
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{
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break;
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}
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wlinfo("Read %ld bytes\n", (long)nread);
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ret = bcmf_core_set_backplane_window(sbus, address);
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if (ret < 0)
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{
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wlerr("ERROR: bcmf_core_set_backplane_window() failed: %d\n", ret);
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goto errout_with_buf;
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}
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total_read = nread;
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/* Transfer firmware data */
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ret = bcmf_transfer_bytes(sbus, true, 1,
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address & SBSDIO_SB_OFT_ADDR_MASK, buf,
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total_read);
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if (ret < 0)
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{
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wlerr("ERROR: Transfer failed address=%lx total_read=%lu: %d\n",
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(unsigned long)address, (unsigned long)total_read, ret);
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goto errout_with_buf;
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}
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address += total_read;
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}
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while (nread == BCMF_UPLOAD_TRANSFER_SIZE);
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file_close(&finfo);
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kmm_free(buf);
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wlinfo("Upload complete\n");
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return OK;
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errout_with_buf:
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kmm_free(buf);
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errout_with_file:
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file_close(&finfo);
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return ret;
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}
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#endif
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int bcmf_upload_nvram(FAR struct bcmf_sdio_dev_s *sbus)
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{
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int ret;
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uint32_t nvram_sz;
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uint32_t token;
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/* Round up the size of the image */
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nvram_sz = (*sbus->chip->nvram_image_size + 63) & (-64);
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wlinfo("nvram size is %d %d bytes\n", nvram_sz,
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*sbus->chip->nvram_image_size);
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/* Write image */
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ret = bcmf_upload_binary(sbus, sbus->chip->ram_size - 4 - nvram_sz,
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sbus->chip->nvram_image,
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*sbus->chip->nvram_image_size);
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if (ret != OK)
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{
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return ret;
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}
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/* Generate length token */
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token = nvram_sz / 4;
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token = (~token << 16) | (token & 0x0000ffff);
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/* Write the length token to the last word */
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ret = bcmf_write_sbreg(sbus, sbus->chip->ram_size - 4,
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(FAR uint8_t *)&token, 4);
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if (ret != OK)
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{
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return ret;
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}
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: bcmf_read_sbreg
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****************************************************************************/
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int bcmf_read_sbreg(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
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FAR uint8_t *reg, unsigned int len)
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{
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int ret = bcmf_core_set_backplane_window(sbus, address);
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if (ret != OK)
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{
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return ret;
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}
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address &= SBSDIO_SB_OFT_ADDR_MASK;
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/* Map to 32-bit access if len == 4 */
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if (len == 4)
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{
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address |= SBSDIO_SB_ACCESS_2_4B_FLAG;
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}
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return bcmf_transfer_bytes(sbus, false, 1, address, reg, len);
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}
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/****************************************************************************
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* Name: bcmf_write_sbreg
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****************************************************************************/
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int bcmf_write_sbreg(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
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FAR uint8_t *reg, unsigned int len)
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{
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int ret = bcmf_core_set_backplane_window(sbus, address);
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if (ret != OK)
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{
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return ret;
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}
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address &= SBSDIO_SB_OFT_ADDR_MASK;
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/* Map to 32-bit access if len == 4 */
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if (len == 4)
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{
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address |= SBSDIO_SB_ACCESS_2_4B_FLAG;
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}
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return bcmf_transfer_bytes(sbus, true, 1, address, reg, len);
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}
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/****************************************************************************
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* Name: bcmf_core_upload_firmware
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****************************************************************************/
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int bcmf_core_upload_firmware(FAR struct bcmf_sdio_dev_s *sbus)
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{
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int ret;
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wlinfo("upload firmware\n");
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/* Disable ARMCM3 core and reset SOCRAM core to set device in firmware
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* upload mode
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*/
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bcmf_core_disable(sbus, WLAN_ARMCM3_CORE_ID);
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bcmf_core_reset(sbus, SOCSRAM_CORE_ID);
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/* Do chip specific initialization */
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if (sbus->cur_chip_id == SDIO_DEVICE_ID_BROADCOM_43430)
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{
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/* Disable remap for SRAM_3. Only for 4343x */
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bcmf_write_sbregw(sbus, SOCSRAM_BANKX_INDEX, 0x3);
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bcmf_write_sbregw(sbus, SOCSRAM_BANKX_PDA, 0);
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}
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up_mdelay(50);
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/* Flash chip firmware */
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#ifdef CONFIG_IEEE80211_BROADCOM_FWFILES
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ret = bcmf_upload_file(sbus, 0, CONFIG_IEEE80211_BROADCOM_FWFILENAME);
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#else
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wlinfo("firmware size is %d bytes\n", *sbus->chip->firmware_image_size);
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ret = bcmf_upload_binary(sbus, 0, sbus->chip->firmware_image,
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*sbus->chip->firmware_image_size);
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#endif
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if (ret < 0)
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{
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wlerr("ERROR: Failed to upload firmware\n");
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return ret;
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}
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/* Flash NVRAM configuration file */
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wlinfo("upload nvram configuration\n");
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ret = bcmf_upload_nvram(sbus);
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if (ret < 0)
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{
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wlerr("ERROR: Failed to upload NVRAM\n");
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return ret;
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}
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/* Firmware upload done, restart ARMCM3 core */
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up_mdelay(10);
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bcmf_core_reset(sbus, WLAN_ARMCM3_CORE_ID);
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/* Check ARMCM3 core is running */
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up_mdelay(10);
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if (!bcmf_core_isup(sbus, WLAN_ARMCM3_CORE_ID))
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{
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wlerr("Cannot start ARMCM3 core\n");
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return -ETIMEDOUT;
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}
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return OK;
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}
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bool bcmf_core_isup(FAR struct bcmf_sdio_dev_s *sbus, unsigned int core)
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{
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uint32_t value = 0;
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uint32_t base;
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if (core >= MAX_CORE_ID)
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{
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wlerr("Invalid core id %d\n", core);
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return false;
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}
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base = sbus->chip->core_base[core];
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bcmf_read_sbregw(sbus, base + BCMA_IOCTL, &value);
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if ((value & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) != BCMA_IOCTL_CLK)
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{
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return false;
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}
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bcmf_read_sbregw(sbus, base + BCMA_RESET_CTL, &value);
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return (value & BCMA_RESET_CTL_RESET) == 0;
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}
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void bcmf_core_disable(FAR struct bcmf_sdio_dev_s *sbus, unsigned int core)
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{
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uint8_t value;
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if (core >= MAX_CORE_ID)
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{
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wlerr("Invalid core id %d\n", core);
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return;
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}
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uint32_t base = sbus->chip->core_base[core];
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/* Check if core is already in reset state */
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bcmf_read_sbregb(sbus, base + BCMA_RESET_CTL, &value);
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if ((value & BCMA_RESET_CTL_RESET) != 0)
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{
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/* Core already disabled */
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return;
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}
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/* Ensure no backplane operation is pending */
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up_mdelay(10);
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/* Set core in reset state */
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bcmf_write_sbregb(sbus, base + BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
|
|
up_udelay(1);
|
|
|
|
/* Write 0 to the IO control and read it back */
|
|
|
|
bcmf_write_sbregb(sbus, base + BCMA_IOCTL, 0);
|
|
bcmf_read_sbregb(sbus, base + BCMA_IOCTL, &value);
|
|
up_udelay(10);
|
|
}
|
|
|
|
void bcmf_core_reset(FAR struct bcmf_sdio_dev_s *sbus, unsigned int core)
|
|
{
|
|
uint32_t value;
|
|
uint32_t base;
|
|
|
|
if (core >= MAX_CORE_ID)
|
|
{
|
|
wlerr("Invalid core id %d\n", core);
|
|
return;
|
|
}
|
|
|
|
base = sbus->chip->core_base[core];
|
|
|
|
/* Put core in reset state */
|
|
|
|
bcmf_core_disable(sbus, core);
|
|
|
|
/* Run initialization sequence */
|
|
|
|
bcmf_write_sbregb(sbus, base + BCMA_IOCTL, BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
|
|
bcmf_read_sbregw(sbus, base + BCMA_IOCTL, &value);
|
|
|
|
bcmf_write_sbregb(sbus, base + BCMA_RESET_CTL, 0);
|
|
bcmf_read_sbregw(sbus, base + BCMA_RESET_CTL, &value);
|
|
|
|
up_udelay(1);
|
|
|
|
bcmf_write_sbregb(sbus, base + BCMA_IOCTL, BCMA_IOCTL_CLK);
|
|
bcmf_read_sbregw(sbus, base + BCMA_IOCTL, &value);
|
|
|
|
up_udelay(1);
|
|
}
|