249 lines
6.2 KiB
C
249 lines
6.2 KiB
C
/****************************************************************************
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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****************************************************************************/
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#ifndef __DRIVERS_WIRELESS_IEEE80211_BCMF_SDIO_REGS_H
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#define __DRIVERS_WIRELESS_IEEE80211_BCMF_SDIO_REGS_H
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#define SDIO_FUNC_0 0
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#define SDIO_FUNC_1 1
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#define SDIO_FUNC_2 2
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#define SDIOD_FBR_SIZE 0x100
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/* io_en */
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#define SDIO_FUNC_ENABLE_1 0x02
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#define SDIO_FUNC_ENABLE_2 0x04
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/* io_rdys */
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#define SDIO_FUNC_READY_1 0x02
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#define SDIO_FUNC_READY_2 0x04
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/* intr_status */
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#define INTR_STATUS_FUNC1 0x2
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#define INTR_STATUS_FUNC2 0x4
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/* Maximum number of I/O funcs */
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#define SDIOD_MAX_IOFUNCS 7
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/* mask of register map */
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#define REG_F0_REG_MASK 0x7FF
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#define REG_F1_MISC_MASK 0x1FFFF
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/* as of sdiod rev 0, supports 3 functions */
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#define SBSDIO_NUM_FUNCTION 3
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/* function 0 vendor specific CCCR registers */
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#define SDIO_CCCR_BRCM_CARDCAP 0xf0
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#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
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#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
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#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
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#define SDIO_CCCR_BRCM_CARDCTRL 0xf1
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#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02
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#define SDIO_CCCR_BRCM_SEPINT 0xf2
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#define SDIO_SEPINT_MASK 0x01
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#define SDIO_SEPINT_OE 0x02
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#define SDIO_SEPINT_ACT_HI 0x04
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/* function 1 miscellaneous registers */
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/* sprom command and status */
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#define SBSDIO_SPROM_CS 0x10000
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/* sprom info register */
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#define SBSDIO_SPROM_INFO 0x10001
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/* sprom indirect access data byte 0 */
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#define SBSDIO_SPROM_DATA_LOW 0x10002
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/* sprom indirect access data byte 1 */
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#define SBSDIO_SPROM_DATA_HIGH 0x10003
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/* sprom indirect access addr byte 0 */
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#define SBSDIO_SPROM_ADDR_LOW 0x10004
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/* sprom indirect access addr byte 0 */
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#define SBSDIO_SPROM_ADDR_HIGH 0x10005
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/* xtal_pu (gpio) output */
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#define SBSDIO_CHIP_CTRL_DATA 0x10006
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/* xtal_pu (gpio) enable */
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#define SBSDIO_CHIP_CTRL_EN 0x10007
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/* rev < 7, watermark for sdio device */
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#define SBSDIO_WATERMARK 0x10008
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/* control busy signal generation */
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#define SBSDIO_DEVICE_CTL 0x10009
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/* SB Address Window Low (b15) */
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#define SBSDIO_FUNC1_SBADDRLOW 0x1000A
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/* SB Address Window Mid (b23:b16) */
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#define SBSDIO_FUNC1_SBADDRMID 0x1000B
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/* SB Address Window High (b31:b24) */
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#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
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/* Frame Control (frame term/abort) */
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#define SBSDIO_FUNC1_FRAMECTRL 0x1000D
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/* Read Frame Terminate */
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#define SFC_RF_TERM (1 << 0)
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/* Write Frame Terminate */
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#define SFC_WF_TERM (1 << 1)
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/* CRC error for write out of sync */
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#define SFC_CRC4WOOS (1 << 2)
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/* Abort all in-progress frames */
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#define SFC_ABORTALL (1 << 3)
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/* ChipClockCSR (ALP/HT ctl/status) */
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#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
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/* Force ALP request to backplane */
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#define SBSDIO_FORCE_ALP 0x01
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/* Force HT request to backplane */
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#define SBSDIO_FORCE_HT 0x02
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/* Force ILP request to backplane */
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#define SBSDIO_FORCE_ILP 0x04
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/* Make ALP ready (power up xtal) */
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#define SBSDIO_ALP_AVAIL_REQ 0x08
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/* Make HT ready (power up PLL) */
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#define SBSDIO_HT_AVAIL_REQ 0x10
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/* Squelch clock requests from HW */
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#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
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/* Status: ALP is ready */
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#define SBSDIO_ALP_AVAIL 0x40
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/* Status: HT is ready */
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#define SBSDIO_HT_AVAIL 0x80
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/* SdioPullUp (on cmd, d0-d2) */
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#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
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/* Write Frame Byte Count Low */
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#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
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/* Write Frame Byte Count High */
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#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
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/* Read Frame Byte Count Low */
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#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
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/* Read Frame Byte Count High */
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#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
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/* MesBusyCtl (rev 11) */
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#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
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/* Sdio Core Rev 12 */
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#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
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#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
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#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
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#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
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#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
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#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
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#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
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#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
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#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
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#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
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#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
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#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
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#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
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#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
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#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
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#define SBSDIO_CLKAV(regval, alponly) \
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(SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
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#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
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#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
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/* function 1 OCP space */
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/* sb offset addr is <= 15 bits, 32k */
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#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
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#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
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/* with b15, maps to 32-bit SB access */
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#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
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/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
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#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
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#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
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#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
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/* Address bits from SBADDR regs */
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#define SBSDIO_SBWINDOW_MASK 0xffff8000
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#endif /* __DRIVERS_WIRELESS_IEEE80211_BCMF_SDIO_REGS_H */
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