236 lines
8.8 KiB
C
236 lines
8.8 KiB
C
/****************************************************************************
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* arch/z80/include/z180/irq.h
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* arch/chip/irq.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly
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* through nuttx/irq.h (via arch/irq.h)
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*/
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#ifndef __ARCH_Z80_INCLUDE_Z180_IRQ_H
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#define __ARCH_Z80_INCLUDE_Z180_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Z180 Interrupts */
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/* Resets */
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/* RST 0 is the power-up interrupt vector */
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#define Z180_RST1 (0) /* RST 1 */
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#define Z180_RST2 (1) /* RST 2 */
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#define Z180_RST3 (2) /* RST 3 */
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#define Z180_RST4 (3) /* RST 4 */
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#define Z180_RST5 (4) /* RST 5 */
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#define Z180_RST6 (5) /* RST 6 */
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#define Z180_RST7 (6) /* RST 7 */
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/* TRAP Interrupt
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*
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* The Z8X180 generates a non-maskable TRAP interrupt when an undefined Op
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* Code fetch occurs. When a TRAP interrupt occurs the Z8X180 operates as
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* follows:
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*
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* 1. The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to 1.
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* 2. The current PC (Program Counter) is saved on the stack.
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* 3. The Z8X180 vectors to logical address 0 (which may or may not be the
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* same as reset which vectors to physical address 0x00000).
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*
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* The state of the UFO (Undefined Fetch Object) bit in ITC allows TRAP
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* manipulation software to correctly adjust the stacked PC, depending on
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* whether the second or third byte of the Op Code generated the TRAP. If
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* UFO is 0, the starting address of the invalid instruction is equal to
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* the stacked PC-1. If UFO is 1, the starting address of the invalid
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* instruction is equal to the stacked PC-2.
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*/
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#define Z180_TRAP (7)
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/* INT0
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*
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* INT0 (only) has 3 different software programmable interrupt response
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* modes<65>Mode 0, Mode 1 and Mode 2.
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*
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* - INT0 Mode 0. During the interrupt acknowledge cycle, an instruction
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* is fetched from the data bus (DO<44>D7) at the rising edge of T3.
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*
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* - INT0 Mode 1. The PC is stacked and instruction execution restarts at
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* logical address 0x0038.
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*
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* - INT0 Mode 2. The restart address is obtained by reading the contents
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* of a table residing in memory. The vector table consists of up to
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* 128 two-byte restart addresses stored in low byte, high byte order.
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*
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* This is similar to normal vector mode interrupts (like INT1 and 2):
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* The 256-bit table address comes from I, however the lower-order 8
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* bits of the vector is fetched from the data bus.
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*/
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#define Z180_INT0 (8)
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/* Vector Interrupts
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*
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* Normal vector interrupts use a vector table with 16 entries (2 bytes
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* per entry). Each entry holds the address of the interrupt handler.
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* The vector table address is determined by 11-bits from the I and IL
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* registers. The vector table must be aligned on 32-byte address
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* boundaries.
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*/
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#define Z180_INT1 (9) /* Vector offset 0: External /INT1 */
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#define Z180_INT2 (10) /* Vector offset 2: External /INT2 */
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#define Z180_PRT0 (11) /* Vector offset 4: PRT channel 0 */
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#define Z180_PRT1 (12) /* Vector offset 6: PRT channel 1 */
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#define Z180_DMA0 (13) /* Vector offset 8: DMA channel 0 */
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#define Z180_DMA1 (14) /* Vector offset 10: DMA Channel 1 */
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#define Z180_CSIO (15) /* Vector offset 12: Clocked serial I/O */
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#define Z180_ASCI0 (16) /* Vector offset 14: Async channel 0 */
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#define Z180_ASCI1 (18) /* Vector offset 16: Async channel 1 */
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#define Z180_UNUSED (19) /* Vector offset 18-20: unused */
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#define Z180_IRQ_SYSTIMER Z180_RST7
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#define NR_IRQS (20)
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/* IRQ Stack Frame Format
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*
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* This stack frame is created on each interrupt. These registers are stored
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* in the TCB to many context switches.
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*/
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#define XCPT_I (0) /* Offset 0: Saved I w/interrupt state in carry */
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#define XCPT_BC (1) /* Offset 1: Saved BC register */
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#define XCPT_DE (2) /* Offset 2: Saved DE register */
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#define XCPT_IX (3) /* Offset 3: Saved IX register */
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#define XCPT_IY (4) /* Offset 4: Saved IY register */
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#define XCPT_SP (5) /* Offset 5: Offset to SP at time of interrupt */
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#define XCPT_HL (6) /* Offset 6: Saved HL register */
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#define XCPT_AF (7) /* Offset 7: Saved AF register */
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#define XCPT_PC (8) /* Offset 8: Offset to PC at time of interrupt */
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#define XCPTCONTEXT_REGS (9)
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#define XCPTCONTEXT_SIZE (2 * XCPTCONTEXT_REGS)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* This is the type of the register save array */
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typedef uint16_t chipreg_t;
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/* Common Area 1 holds the code and data that is unique to a particular task
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* and shared by all pthreads created from that task. Each task will then
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* have its own copy of struct z180_cbr_s. This structure is created with
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* a reference count of one when the task is created.
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*
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* When the task creates additional threads, the reference count is
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* incremented and the CBR value is shared. When each thread exits, the
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* reference count id decremented. When the reference count is decremented,
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* the physical memory underlying the CBR is finally released.
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*/
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struct z180_cbr_s
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{
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uint8_t cbr; /* The CBR value used by the thread */
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uint8_t crefs; /* The number of task groups using this CBR value (0 or 1) */
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uint8_t pages; /* The number of 4KB pages of physical memory in the allocation */
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};
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/* This struct defines the way the registers and z180-state information are
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* stored.
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*/
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struct xcptcontext
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{
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/* Register save area */
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chipreg_t regs[XCPTCONTEXT_REGS];
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/* The following function pointer is non-zero if there
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* are pending signals to be processed.
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*/
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#ifndef CONFIG_DISABLE_SIGNALS
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CODE void *sigdeliver; /* Actual type is sig_deliver_t */
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/* The following retains that state during signal execution */
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uint16_t saved_pc; /* Saved return address */
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uint16_t saved_i; /* Saved interrupt state */
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#endif
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};
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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EXTERN irqstate_t irqsave(void) __naked;
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EXTERN void irqrestore(irqstate_t flags) __naked;
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_Z80_INCLUDE_Z180_IRQ_H */
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