Fix the Mixed case identifier errors found on sama5 family Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
188 lines
5.9 KiB
C
188 lines
5.9 KiB
C
/****************************************************************************
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* boards/arm/sama5/sama5d3x-ek/src/nor_main.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdio.h>
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#include <debug.h>
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#include <nuttx/cache.h>
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#include <arch/irq.h>
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#include "arm_arch.h"
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#include "mmu.h"
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#include "cp15_cacheops.h"
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#include "sam_periphclks.h"
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#include "hardware/sam_hsmc.h"
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#include "hardware/sam_matrix.h"
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#include "hardware/sam_aximx.h"
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#include "sama5d3x-ek.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define NOR_ENTRY ((nor_entry_t)SAM_EBICS0_VSECTION)
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#define NOR_WAIT 1
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#define NOR_NO_WAIT 0
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#ifdef CONFIG_SAMA5D3XEK_NOR_START
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# define NOR_BOOT_MODE NOR_NO_WAIT
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#else
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# define NOR_BOOT_MODE NOR_WAIT
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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typedef void (*nor_entry_t)(void);
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: nor_main
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*
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* Description:
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* nor_main is a tiny program that runs in ISRAM. nor_main will enable
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* NOR flash then jump to the program in NOR flash
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*
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****************************************************************************/
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int nor_main(int argc, char *argv)
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{
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uint32_t regval;
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/* Here we have a in memory value we can change in the debugger
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* to begin booting in NOR Flash
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*/
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static volatile uint32_t wait = NOR_BOOT_MODE;
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printf("Configuring NOR FLASH on CS0 and %s\n",
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wait ? "waiting" : "booting");
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/* Make sure that the SMC peripheral is enabled (But of course it is... we
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* are executing from NOR FLASH now).
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*/
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sam_hsmc_enableclk();
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/* The SAMA5D3x-EK has 118MB of 16-bit NOR FLASH at CS0. The NOR FLASH
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* has already been configured by the first level ROM bootloader... we
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* simply need to modify the timing here.
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*/
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regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(0) |
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HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(0);
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putreg32(regval, SAM_HSMC_SETUP(HSMC_CS0));
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regval = HSMC_PULSE_NWE_PULSE(10) | HSMC_PULSE_NCS_WRPULSE(10) |
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HSMC_PULSE_NRD_PULSE(11) | HSMC_PULSE_NCS_RDPULSE(11);
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putreg32(regval, SAM_HSMC_PULSE(HSMC_CS0));
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regval = HSMC_CYCLE_NWE_CYCLE(11) | HSMC_CYCLE_NRD_CYCLE(14);
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putreg32(regval, SAM_HSMC_CYCLE(HSMC_CS0));
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regval = HSMC_TIMINGS_TCLR(0) | HSMC_TIMINGS_TADL(0) |
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HSMC_TIMINGS_TAR(0) | HSMC_TIMINGS_TRR(0) |
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HSMC_TIMINGS_TWB(0) | HSMC_TIMINGS_RBNSEL(0);
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putreg32(regval, SAM_HSMC_TIMINGS(HSMC_CS0));
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regval = HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE |
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HSMC_MODE_EXNWMODE_DISABLED | HSMC_MODE_BIT_16 |
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HSMC_MODE_TDFCYCLES(1);
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putreg32(regval, SAM_HSMC_MODE(HSMC_CS0));
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/* Interrupts must be disabled through the following.
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* In this configuration, there should only be timer interrupts.
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* Your NuttX configuration must use CONFIG_SERIAL_LOWCONSOLE=y or printf()
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* will hang when the interrupts are disabled!
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*/
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up_irq_save();
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/* Disable MATRIX write protection */
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#if 0 /* Disabled on reset */
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putreg32(MATRIX_WPMR_WPKEY, SAM_MATRIX_WPMR);
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#endif
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/* Set remap state 1.
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*
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* Boot state: ROM is seen at address 0x00000000
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* Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave
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* interface) instead of ROM.
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* Remap State 1: HEBI is seen at address 0x00000000 (through AHB slave
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* interface) instead of ROM for external boot.
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*
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* REVISIT: This does not work. No matter what I do, the internal
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* SRAM is always visible at address zero. I am missing something.
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*/
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putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR); /* Enable remap */
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putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap HEBI */
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/* Restore MATRIX write protection */
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#if 0 /* Disabled on reset */
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putreg32(MATRIX_WPMR_WPKEY | MATRIX_WPMR_WPEN, SAM_MATRIX_WPMR);
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#endif
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/* Disable the caches and the MMU. Disabling the MMU should be safe here
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* because there is a 1-to-1 identity mapping between the physical and
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* virtual addressing.
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*/
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/* NOTE: This generates crashes and lots of error, but does leave the
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* system in the proper state to run from NOR: very ugly but usable.
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* Better than the alternative.
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*/
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cp15_disable_mmu();
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up_disable_icache();
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up_disable_dcache();
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/* Invalidate caches and TLBs */
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up_invalidate_icache_all();
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up_invalidate_dcache_all();
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cp15_invalidate_tlbs();
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/* Then jump into NOR flash */
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while (wait)
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{
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}
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NOR_ENTRY();
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return 0; /* We should not get here in either case */
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}
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