194 lines
7.7 KiB
C
194 lines
7.7 KiB
C
/************************************************************************************
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* configs/stm3220g-eval/src/stm32_selectsram.c
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "stm32.h"
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#include "stm3220g-eval.h"
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#ifdef CONFIG_STM32_FSMC
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#if STM32_NGPIO_PORTS < 6
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# error "Required GPIO ports not enabled"
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#endif
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/* SRAM Timing */
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#define SRAM_ADDRESS_SETUP_TIME 3
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#define SRAM_ADDRESS_HOLD_TIME 0
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#define SRAM_DATA_SETUP_TIME 6
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#define SRAM_BUS_TURNAROUND_DURATION 1
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#define SRAM_CLK_DIVISION 0
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#define SRAM_DATA_LATENCY 0
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/* SRAM pin definitions */
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#define SRAM_NADDRLINES 21
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#define SRAM_NDATALINES 16
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Private Data
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************************************************************************************/
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/* GPIOs Configuration **************************************************************
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* PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10
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* PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11
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* PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12
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* PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13
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* PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14
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* PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15
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* PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2
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* PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7
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* PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8
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* PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9
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* PD14 <-> FSMC_D0 PE13 <-> FSMC_D10
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* PD15 <-> FSMC_D1 PE14 <-> FSMC_D11
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* PE15 <-> FSMC_D12
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*/
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/* GPIO configurations unique to SRAM */
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static const uint32_t g_sramconfig[] =
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{
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/* NE3, NBL0, NBL1, */
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GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2
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};
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#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t))
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: stm32_selectsram
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*
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* Description:
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* Initialize to access external SRAM. SRAM will be visible at the FSMC Bank
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* NOR/SRAM2 base address (0x64000000)
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*
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* General transaction rules. The requested AHB transaction data size can be 8-,
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* 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data width. Some simple
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* transaction rules must be followed:
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*
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* Case 1: AHB transaction width and SRAM data width are equal
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* There is no issue in this case.
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* Case 2: AHB transaction size is greater than the memory size
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* In this case, the FSMC splits the AHB transaction into smaller consecutive
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* memory accesses in order to meet the external data width.
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* Case 3: AHB transaction size is smaller than the memory size.
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* SRAM supports the byte select feature.
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* a) FSMC allows write transactions accessing the right data through its
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* byte lanes (NBL[1:0])
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* b) Read transactions are allowed (the controller reads the entire memory
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* word and uses the needed byte only). The NBL[1:0] are always kept low
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* during read transactions.
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*
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************************************************************************************/
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void stm32_selectsram(void)
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{
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/* Configure new GPIO pins */
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stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */
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stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */
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stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */
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/* Enable AHB clocking to the FSMC */
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stm32_enablefsmc();
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/* Bank1 NOR/SRAM control register configuration
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*
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* Bank enable : Not yet
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* Data address mux : Disabled
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* Memory Type : PSRAM
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* Data bus width : 16-bits
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* Flash access : Disabled
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* Burst access mode : Disabled
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* Polarity : Low
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* Wrapped burst mode : Disabled
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* Write timing : Before state
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* Write enable : Yes
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* Wait signal : Disabled
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* Extended mode : Disabled
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* Asynchronous wait : Disabled
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* Write burst : Disabled
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*/
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putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) |
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FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) |
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FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) |
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FSMC_BTR_ACCMODA),
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STM32_FSMC_BTR2);
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/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
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putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */
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/* Enable the bank */
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putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2);
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}
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#endif /* CONFIG_STM32_FSMC */
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