30a01ab551
FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) |
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:164:42: note: expanded from macro 'FSMC_BTR_ADDHLD'
^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'
^
Error: board/stm32_selectsram.c:166:13: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value]
FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) |
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:176:42: note: expanded from macro 'FSMC_BTR_CLKDIV'
^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'
^
Error: board/stm32_selectsram.c:167:13: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value]
FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) |
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:180:42: note: expanded from macro 'FSMC_BTR_DATLAT'
^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
184 lines
6.8 KiB
C
184 lines
6.8 KiB
C
/****************************************************************************
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* boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include "chip.h"
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#include "arm_internal.h"
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#include "stm32.h"
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#include "stm3240g-eval.h"
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#ifdef CONFIG_STM32_FSMC
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#if STM32_NGPIO_PORTS < 6
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# error "Required GPIO ports not enabled"
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#endif
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/* SRAM Timing */
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#define SRAM_ADDRESS_SETUP_TIME 3
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#define SRAM_ADDRESS_HOLD_TIME 1
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#define SRAM_DATA_SETUP_TIME 6
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#define SRAM_BUS_TURNAROUND_DURATION 1
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#define SRAM_CLK_DIVISION 1
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#define SRAM_DATA_LATENCY 2
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/* SRAM pin definitions */
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#define SRAM_NADDRLINES 21
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#define SRAM_NDATALINES 16
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* GPIOs Configuration ******************************************************
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* PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10
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* PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11
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* PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12
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* PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13
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* PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14
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* PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15
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* PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2
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* PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7
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* PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8
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* PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9
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* PD14 <-> FSMC_D0 PE13 <-> FSMC_D10
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* PD15 <-> FSMC_D1 PE14 <-> FSMC_D11
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* PE15 <-> FSMC_D12
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*/
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/* GPIO configurations unique to SRAM */
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static const uint32_t g_sramconfig[] =
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{
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/* NE3, NBL0, NBL1, */
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GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2
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};
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#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t))
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_selectsram
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*
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* Description:
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* Initialize to access external SRAM. SRAM will be visible at the FSMC
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* Bank NOR/SRAM2 base address (0x64000000)
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*
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* General transaction rules. The requested AHB transaction data size can
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* be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data
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* width. Some simple transaction rules must be followed:
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*
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* Case 1: AHB transaction width and SRAM data width are equal
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* There is no issue in this case.
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* Case 2: AHB transaction size is greater than the memory size
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* In this case, the FSMC splits the AHB transaction into smaller
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* consecutive memory accesses in order to meet the external data width.
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* Case 3: AHB transaction size is smaller than the memory size.
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* SRAM supports the byte select feature.
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* a) FSMC allows write transactions accessing the right data through its
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* byte lanes (NBL[1:0])
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* b) Read transactions are allowed (the controller reads the entire
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* memory word and uses the needed byte only). The NBL[1:0] are always
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* kept low during read transactions.
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*
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****************************************************************************/
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void stm32_selectsram(void)
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{
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/* Configure new GPIO pins */
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stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */
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stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */
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stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */
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/* Enable AHB clocking to the FSMC */
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stm32_fsmc_enable();
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/* Bank1 NOR/SRAM control register configuration
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*
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* Bank enable : Not yet
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* Data address mux : Disabled
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* Memory Type : PSRAM
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* Data bus width : 16-bits
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* Flash access : Disabled
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* Burst access mode : Disabled
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* Polarity : Low
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* Wrapped burst mode : Disabled
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* Write timing : Before state
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* Write enable : Yes
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* Wait signal : Disabled
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* Extended mode : Disabled
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* Asynchronous wait : Disabled
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* Write burst : Disabled
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*/
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putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 |
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FSMC_BCR_WREN), STM32_FSMC_BCR2);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) |
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FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) |
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FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) |
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FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) |
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FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) |
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FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) |
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FSMC_BTR_ACCMODA),
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STM32_FSMC_BTR2);
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/* Bank1 NOR/SRAM timing register for write configuration,
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* if extended mode is used
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*/
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putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */
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/* Enable the bank */
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putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM |
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FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2);
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}
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#endif /* CONFIG_STM32_FSMC */
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