Ville Juven ae64f28344 RISC-V: Implement simple and native NuttX SBI ... This is a minimalistic SBI implementation for NuttX. Provides a single service for now: - Access to machine timer Provides a start trampoline to start NuttX in S-mode: - Exceptions / faults are delegated to S-mode. - External interrupts are delegated to S-mode. Machine mode timer is used as follows: - The timer compare match register reload happens in M-mode, via call gate "riscv_sbi_set_timer" - The compare match event is dispatched to S-mode ISR, which will notify the kernel to advance time - Clearing the STIP interrupt does not work from S-mode, so the call gate does this from M-mode The only supported (tested) target for now is MPFS.		2023-06-07 01:48:15 +08:00
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include	arch/risc-v: change up_saveusercontext to assembly code	2023-04-27 17:34:30 +08:00
src	RISC-V: Implement simple and native NuttX SBI	2023-06-07 01:48:15 +08:00
Kconfig	RISC-V: Implement simple and native NuttX SBI	2023-06-07 01:48:15 +08:00