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nuttx/arch/risc-v/Kconfig
Yanfeng Liu 75d0c2946d risc-v: Initial support for CanMV-k230 board and K230 chip 
The code is mainly derived from the NuttX qemu-rv/rv-virt codebase.

Major changes:

- boards/Kconfig:       add new BOARD_K230_CANMV
- arch/risc-v/Kconfig:  add new CHIP_K230 chip and ARCH_RV_MMIO_BITS
- arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to
                        select MMIO access width

New additions:

- arch/risc-v/include/k230/: k230 SoC definitions
- arch/risc-v/src/k230/:     k230 SoC sources
- boards/risc-v/k230/canmv230/:  CanMV-K230 board sources and configs
- Documentation/platforms/risc-v/k230/: simple doc

Note that only FLAT build works for canmv230 now.

This PR has changes in RiscV common layer thus may affect other RiscV ports
It changes the mtime/mtimecmp access control from using config ARCH_RV64 to
newly intorduced config ARCH_RV_MMIO_BITS.

Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this
can't cope with the situation with K230 --- it has ARCH_RV64 but only can do
32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value
depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/
RV64 respectively. This allows the macro to replace current use of ARCH_RV64
in riscv_mtimer.c.

The new MMIO_BITS config is a derived one, and for RiscV chips with
equal CPU and MMIO widths there is no need to explicitly set it as the
default rule will do that. Only chips with different CPU and MMIO widths
need set it in Kconfig.

So by design this change should be safe but RiscV ports should be checked.

"ostest" verification has been done for:

- canmv230/nsh
- rv-vivt/nsh
- rv-virt/nsh64

configuration generation and manual check of derived RV_MMIO_BITS has been
done for:

- star64/nsh
- arty_a7/nsh
- bl602evb/nsh

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2023-12-17 01:10:57 -08:00

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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_RISCV
comment "RISC-V Options"
choice
prompt "RISC-V chip selection"
default ARCH_CHIP_RISCV_CUSTOM
config ARCH_CHIP_FE310
bool "SiFive FE310"
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ONESHOT
select ALARM_ARCH
---help---
SiFive FE310 processor (E31 RISC-V Core with MAC extensions).
config ARCH_CHIP_K210
bool "Kendryte K210"
select ARCH_RV64
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_FPU if !K210_WITH_QEMU
select ARCH_HAVE_DPFPU if !K210_WITH_QEMU
select ARCH_HAVE_MPU
select ARCH_HAVE_TESTSET
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_MISALIGN_EXCEPTION
select ONESHOT
select ALARM_ARCH
---help---
Kendryte K210 processor (RISC-V 64bit core with GC extensions)
config ARCH_CHIP_LITEX
bool "Enjoy Digital LITEX VEXRISCV"
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_DCACHE
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_RESET
---help---
Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
config ARCH_CHIP_BL602
bool "BouffaloLab BL602"
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_RESET
select ARCH_HAVE_MISALIGN_EXCEPTION
select ONESHOT
select ALARM_ARCH
---help---
BouffaloLab BL602(rv32imfc)
config ARCH_CHIP_ESP32C3
bool "Espressif ESP32-C3"
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_C
select ARCH_VECNOTIRQ
select ARCH_HAVE_MPU
select ARCH_HAVE_RESET
select LIBC_ARCH_ATOMIC
select LIBC_ARCH_MEMCPY
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
select LIBC_ARCH_MEMMOVE
select LIBC_ARCH_MEMSET
select LIBC_ARCH_STRCHR
select LIBC_ARCH_STRCMP
select LIBC_ARCH_STRCPY
select LIBC_ARCH_STRLCPY
select LIBC_ARCH_STRNCPY
select LIBC_ARCH_STRLEN
select LIBC_ARCH_STRNLEN
select ARCH_HAVE_TEXT_HEAP
select ARCH_HAVE_BOOTLOADER
select ARCH_HAVE_PERF_EVENTS
---help---
Espressif ESP32-C3 (RV32IMC).
config ARCH_CHIP_ESP32C6
bool "Espressif ESP32-C6"
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_VECNOTIRQ
select ARCH_HAVE_RESET
select LIBC_ARCH_MEMCPY
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
select LIBC_ARCH_MEMMOVE
select LIBC_ARCH_MEMSET
select LIBC_ARCH_STRCHR
select LIBC_ARCH_STRCMP
select LIBC_ARCH_STRCPY
select LIBC_ARCH_STRLCPY
select LIBC_ARCH_STRNCPY
select LIBC_ARCH_STRLEN
select LIBC_ARCH_STRNLEN
---help---
Espressif ESP32-C6 (RV32IMAC).
config ARCH_CHIP_ESPRESSIF
bool "Espressif ESP32 family"
---help---
Family of RISC-V based microcontrollers from Espressif Systems.
config ARCH_CHIP_C906
bool "THEAD C906"
select ARCH_RV64
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MPU
select ONESHOT
select ALARM_ARCH
---help---
THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
config ARCH_CHIP_MPFS
bool "MicroChip Polarfire (MPFS)"
select ARCH_RV64
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MPU
select ARCH_HAVE_MMU
select ARCH_MMU_TYPE_SV39
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
select ARCH_HAVE_RESET
select ARCH_HAVE_SPI_CS_CONTROL
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_S_MODE
select ONESHOT
select ALARM_ARCH
---help---
MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).
config ARCH_CHIP_RV32M1
bool "NXP RV32M1"
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_C
---help---
NXP RV32M1 processor (RISC-V Core with PULP extensions).
config ARCH_CHIP_QEMU_RV
bool "QEMU RV"
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_MPU
select ARCH_HAVE_MMU
select ARCH_MMU_TYPE_SV39 if ARCH_CHIP_QEMU_RV64
select ARCH_MMU_TYPE_SV32 if ARCH_CHIP_QEMU_RV32
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
select ARCH_HAVE_S_MODE
select ONESHOT
select ALARM_ARCH
---help---
QEMU Generic RV32/RV64 processor
config ARCH_CHIP_HPM6750
bool "Hpmicro HPM6750"
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ONESHOT
select ALARM_ARCH
---help---
Hpmicro HPM6750 processor (D45 RISC-V Core with MAC extensions).
config ARCH_CHIP_JH7110
bool "StarFive JH7110"
select ARCH_RV64
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_MPU
select ARCH_HAVE_MMU
select ARCH_MMU_TYPE_SV39
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
select ARCH_HAVE_S_MODE
select ONESHOT
select ALARM_ARCH
---help---
StarFive JH7110 SoC.
config ARCH_CHIP_BL808
bool "Bouffalo Lab BL808"
select ARCH_RV64
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_MPU
select ARCH_HAVE_MMU
select ARCH_MMU_TYPE_SV39
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
select ARCH_HAVE_S_MODE
select ONESHOT
select ALARM_ARCH
---help---
Bouffalo Lab BL808 SoC.
config ARCH_CHIP_K230
bool "Kendryte K230"
select ARCH_RV64
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MISALIGN_EXCEPTION
select ARCH_HAVE_MPU
select ARCH_HAVE_MMU
select ARCH_MMU_TYPE_SV39
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
select ARCH_HAVE_S_MODE
select ONESHOT
select ALARM_ARCH
---help---
Kendryte K230 SoC (RV64GCV and RV64GCVX C908 cores).
config ARCH_CHIP_RISCV_CUSTOM
bool "Custom RISC-V chip"
select ARCH_CHIP_CUSTOM
---help---
Select this option if there is no directory for the chip under arch/risc-v/src/.
endchoice
config ARCH_RV32
bool
default n
config ARCH_RV64
bool
default n
select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
config ARCH_RV_ISA_M
bool
default n
config ARCH_RV_ISA_A
bool
default n
select ARCH_HAVE_TESTSET
config ARCH_RV_ISA_C
bool
default n
config ARCH_RV_MMIO_BITS
int
# special cases
default 32 if ARCH_CHIP_K230
# general fallbacks
default 32 if ARCH_RV32
default 64 if ARCH_RV64
config ARCH_FAMILY
string
default "rv32" if ARCH_RV32
default "rv64" if ARCH_RV64
config ARCH_CHIP
string
default "fe310" if ARCH_CHIP_FE310
default "k210" if ARCH_CHIP_K210
default "litex" if ARCH_CHIP_LITEX
default "bl602" if ARCH_CHIP_BL602
default "esp32c3" if ARCH_CHIP_ESP32C3
default "esp32c6" if ARCH_CHIP_ESP32C6
default "espressif" if ARCH_CHIP_ESPRESSIF
default "c906" if ARCH_CHIP_C906
default "mpfs" if ARCH_CHIP_MPFS
default "rv32m1" if ARCH_CHIP_RV32M1
default "qemu-rv" if ARCH_CHIP_QEMU_RV
default "hpm6750" if ARCH_CHIP_HPM6750
default "jh7110" if ARCH_CHIP_JH7110
default "bl808" if ARCH_CHIP_BL808
default "k230" if ARCH_CHIP_K230
config ARCH_RISCV_INTXCPT_EXTENSIONS
bool "RISC-V Integer Context Extensions"
default n
depends on RV32M1_OPENISA_TOOLCHAIN
---help---
RISC-V could be customized with extensions. Some Integer Context
Registers have to be saved and restored when Contexts switch.
if ARCH_RISCV_INTXCPT_EXTENSIONS
config ARCH_RISCV_INTXCPT_EXTREGS
int "Number of Extral RISC-V Integer Context Registers"
default 0
endif
config ARCH_MMU_TYPE_SV39
bool
default n
config ARCH_MMU_TYPE_SV32
bool
default n
config ARCH_HAVE_S_MODE
bool
default n
config ARCH_HAVE_MISALIGN_EXCEPTION
bool
default n
---help---
The chip will raise a exception while misaligned memory access.
config RISCV_MISALIGNED_HANDLER
bool "Software misaligned memory access handler"
depends on ARCH_HAVE_MISALIGN_EXCEPTION
default y
# Option to run NuttX in supervisor mode. This is obviously not usable in
# flat mode, is questionable in protected mode, but is mandatory in kernel
# mode.
#
# Kernel mode requires this as M-mode uses flat addressing and the kernel
# memory must be mapped in order to share memory between the kernel and
# different user tasks which reside in virtual memory.
#
# Note that S-mode requires a companion software (SBI)
#
config ARCH_USE_S_MODE
bool "Run the NuttX kernel in S-mode"
default n
depends on ARCH_HAVE_S_MODE && BUILD_KERNEL && ARCH_USE_MMU
---help---
Most of the RISC-V implementations run in M-mode (flat addressing)
and/or U-mode (in case of separate kernel-/userspaces). This provides
an option to run the kernel in S-mode, if the target supports it.
choice
prompt "Toolchain Selection"
default RISCV_TOOLCHAIN_GNU_RV64
config RISCV_TOOLCHAIN_GNU_RV64
bool "Generic GNU RV64 toolchain"
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 5.2 or newer)
configured for riscv64-unknown-elf.
config RISCV_TOOLCHAIN_GNU_RV32
bool "Generic GNU RV32 toolchain"
select ARCH_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 5.2 or newer)
configured for riscv32-unknown-elf.
endchoice
config RISCV_SEMIHOSTING_HOSTFS
bool "Semihosting HostFS"
depends on FS_HOSTFS
---help---
Mount HostFS through semihosting.
This doesn't support some directory operations like readdir because
of the limitations of semihosting mechanism.
if RISCV_SEMIHOSTING_HOSTFS
config RISCV_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
bool "Cache coherence in semihosting hostfs"
depends on ARCH_DCACHE
---help---
Flush & Invalidte cache before & after bkpt instruction.
endif
if ARCH_CHIP_LITEX
choice
prompt "LITEX Core Selection"
default LITEX_CORE_VEXRISCV
config LITEX_CORE_VEXRISCV
bool "vexriscv core"
config LITEX_CORE_VEXRISCV_SMP
bool "vexriscv_smp core"
select ARCH_HAVE_MPU
select ARCH_HAVE_MMU
select ARCH_RV_ISA_C
select ARCH_MMU_TYPE_SV32
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
select ARCH_HAVE_S_MODE
select ARCH_HAVE_ELF_EXECUTABLE
endchoice
endif
source "arch/risc-v/src/opensbi/Kconfig"
source "arch/risc-v/src/nuttsbi/Kconfig"
if ARCH_CHIP_FE310
source "arch/risc-v/src/fe310/Kconfig"
endif
if ARCH_CHIP_K210
source "arch/risc-v/src/k210/Kconfig"
endif
if ARCH_CHIP_LITEX
source "arch/risc-v/src/litex/Kconfig"
endif
if ARCH_CHIP_BL602
source "arch/risc-v/src/bl602/Kconfig"
endif
if ARCH_CHIP_ESP32C3
source "arch/risc-v/src/esp32c3/Kconfig"
endif
if ARCH_CHIP_ESP32C6
source "arch/risc-v/src/esp32c6/Kconfig"
endif
if ARCH_CHIP_ESPRESSIF
source "arch/risc-v/src/espressif/Kconfig"
endif
if ARCH_CHIP_C906
source "arch/risc-v/src/c906/Kconfig"
endif
if ARCH_CHIP_MPFS
source "arch/risc-v/src/mpfs/Kconfig"
endif
if ARCH_CHIP_RV32M1
source "arch/risc-v/src/rv32m1/Kconfig"
endif
if ARCH_CHIP_QEMU_RV
source "arch/risc-v/src/qemu-rv/Kconfig"
endif
if ARCH_CHIP_HPM6750
source "arch/risc-v/src/hpm6750/Kconfig"
endif
if ARCH_CHIP_JH7110
source "arch/risc-v/src/jh7110/Kconfig"
endif
if ARCH_CHIP_BL808
source "arch/risc-v/src/bl808/Kconfig"
endif
if ARCH_CHIP_K230
source "arch/risc-v/src/k230/Kconfig"
endif
endif
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