nuttx/arch/arm/include/samd5e5/irq.h
Gregory Nutt a9d713bbcc This is the initial commit the port to the SAMD5x/E5x MCU family and also support for the Adafruit Metro M4 board. It port is untested and unfinished. It currently will not even link due to some missing clock related logic.
Squashed commit of the following:

    arch/arm/src/samd5e5: Clean-up EIC logic.
    arch/arm/src/samd5e5:  Fix some compilation issues; Still issues with the EIC logic from samd2x.
    arch/arm/src/samd5e5:  Fix some compilation issues; bring in some EIC logic from samd2x.
    arch/arm/src/samd5e5:  Add NVMCTRL header file, fix some compiler problems, misc. clean-up.
    configs/metro-m4:  Add LED support.
    arch/arm/src/samd5e5:  Bring in SAML21 clock configuration.  This is a WIP; it cannot possible even compile yet.
    arch/arm/src/samd5e5:  Leverage Cortex-M4 interrupt and SysTick logic from the SAM3/4.
    arch/arm/src/samd5e5: Add SERCOM utility function.
    arch/arm/src/samd5e5:  Bring all SERCOM USART logic from SAMD2L2 to SAMD5E5.  This is a brute coy with nothing more than more that name changes and extension from 5 to 7 SERCOMs.
    arch/arm/src/samd5e5: Add sam_config.h header file
    arch/arm/src/samd5e5/:  Add Generic Clock (GCLK) utility functions.
    arch/arm/src/samd5e5:  Add EVSYS register definition file
    arch/arm/src/samd5e5 and configs/metro-m4:  Use SERCOM3 for the Arduino serial shield as console.
    arch/arm/src/samd5e5/chip:  Add SERCOM USART, SPI, I2C master, and slave register defintions header files
    arch/arm/src/samd5e5/chip:  Add AES, PM, TRNG, and WDT header files.
    arch/arm/src/samd5e5/chip:  Add pin multiplexing header files.
    Various fixes to configuration system; fix metro-m4/nsh defconfig file.
    configs/metro-m4:  Add initial support for the Adafruit Metro M4 board.
    arch/arm/src/samd5e5:  Add peripheral clock helpers.
    arch/arm/src/samd5e5/chip:  Add PAC register definition header file.  Fix some errors in the memory map header file.
    arch/arm/src/samd5e5:  Add chip.h headerf file.
    arch/arm/src/samd5e5:  Add PORT register definitions and support from SAML21.
    arch/arm/include/samd5e5:  Add interrupt vector definitions.
    arch/arm/src/samd5e5:  Add some boilerplate files.  Correct some typos.
    arch/arm/src/samd5e5/chip/sam_eic.h:  Add EIC register definitions.
    arch/arm/src/samd5e5/chip:  Add OSC32KCTRL and OSCCTRL register definitions.
    arch/arm/src/samd5e5/chip:  Add GCLK, MCLK, and RSTC header files.
    arch/arm/src/samd5e5/chip/sam_cmcc.h:  Add CMCC register definitions
    arch/arm/src/samd5e5/chip/sam_supc.h:  Add SUPC header file.
    arch/arm/src/samd5e5:  Add start-up logic.
    arch/arm/src/samd5e5:  Add Make.defs file
    arch/arm/src/samd5e5/chip:  Add memory map header file.
    arch/arm/include/samd5e5:  Add chip.h header file.
    arch/arm/Kconfig and arch/arm/src/samd5e5/Kconfig:  Add configuration logic for the SAMD5x/Ex family.
2018-07-26 12:12:08 -06:00

114 lines
4.7 KiB
C

/****************************************************************************************
* arch/arm/include/samd5e5/irq.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/samd5e5/chip.h>
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define SAM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define SAM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define SAM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define SAM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define SAM_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define SAM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define SAM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define SAM_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* Chip-Specific External interrupts */
#define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
# include <arch/samd5e5/samd5e5_irq.h>
#else
# error "Unsupported SAMD5/E5 family"
#endif
/****************************************************************************************
* Public Types
****************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H */