187 lines
11 KiB
C
187 lines
11 KiB
C
/****************************************************************************
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* arch/arm/include/xmc4/xmc4500_irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H
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#define xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in the file nuttx/arch/arm/include/kinets/irq.h which includes this file
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*
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* External interrupts (vectors >= 16)
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*
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* Acronyms:
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* ADC - Analog to Digital Converter
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* CCU - Capture Compare Unit
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* DAC - Digital to Analog Converter
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* DSD - Delta Sigmoid Demodulator
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* ERU - External Request Unit
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* FCE - Flexible CRC Engine
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* GPDMA - General Purpose DMA
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* LEDTS - LED and Touch Sense Control Unit
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* PMU - Program Management Unit
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* POSIF - Position Interface
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* SDMMC - Multi Media Card Interface
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* USB - Universal Serial Bus
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* USCI - Universal Serial Interface
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*/
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#define XMC4_IRQ_SCU (XMC4_IRQ_FIRST + 0) /* 0: System Control */
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#define XMC4_IRQ_ERU0_SR0 (XMC4_IRQ_FIRST + 1) /* 1: ERU0, SR0 */
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#define XMC4_IRQ_ERU0_SR1 (XMC4_IRQ_FIRST + 2) /* 2: ERU0, SR1 */
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#define XMC4_IRQ_ERU0_SR2 (XMC4_IRQ_FIRST + 3) /* 3: ERU0, SR2 */
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#define XMC4_IRQ_ERU0_SR3 (XMC4_IRQ_FIRST + 4) /* 4: ERU0, SR3 */
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#define XMC4_IRQ_ERU1_SR0 (XMC4_IRQ_FIRST + 5) /* 5: ERU1, SR0 */
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#define XMC4_IRQ_ERU1_SR1 (XMC4_IRQ_FIRST + 6) /* 6: ERU1, SR1 */
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#define XMC4_IRQ_ERU1_SR2 (XMC4_IRQ_FIRST + 7) /* 7: ERU1, SR2 */
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#define XMC4_IRQ_ERU1_SR3 (XMC4_IRQ_FIRST + 8) /* 8: ERU1, SR3 */
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#define XMC4_IRQ_RESVD009 (XMC4_IRQ_FIRST + 9) /* 9: Reserved */
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#define XMC4_IRQ_RESVD010 (XMC4_IRQ_FIRST + 10) /* 10: Reserved */
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#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST + 11) /* 11: Reserved */
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#define XMC4_IRQ_PMU1_SR0 (XMC4_IRQ_FIRST + 12) /* 12: PMU, SR0 */
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#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST + 13) /* 13: Reserved */
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#define XMC4_IRQ_VADC_COSR0 (XMC4_IRQ_FIRST + 14) /* 14: ADC Common Block 0 */
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#define XMC4_IRQ_VADC_COSR1 (XMC4_IRQ_FIRST + 15) /* 15: ADC Common Block 1 */
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#define XMC4_IRQ_VADC_COSR2 (XMC4_IRQ_FIRST + 16) /* 16: ADC Common Block 2 */
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#define XMC4_IRQ_VADC_COSR3 (XMC4_IRQ_FIRST + 17) /* 17: ADC Common Block 3 */
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#define XMC4_IRQ_VADC_GOSR0 (XMC4_IRQ_FIRST + 18) /* 18: ADC Group 0, SR0 */
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#define XMC4_IRQ_VADC_GOSR1 (XMC4_IRQ_FIRST + 19) /* 19: ADC Group 0, SR1 */
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#define XMC4_IRQ_VADC_GOSR2 (XMC4_IRQ_FIRST + 20) /* 20: ADC Group 0, SR2 */
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#define XMC4_IRQ_VADC_GOSR3 (XMC4_IRQ_FIRST + 21) /* 21: ADC Group 0, SR3 */
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#define XMC4_IRQ_VADC_G1SR0 (XMC4_IRQ_FIRST + 22) /* 22: ADC Group 1, SR0 */
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#define XMC4_IRQ_VADC_G1SR1 (XMC4_IRQ_FIRST + 23) /* 23: ADC Group 1, SR1 */
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#define XMC4_IRQ_VADC_G1SR2 (XMC4_IRQ_FIRST + 24) /* 24: ADC Group 1, SR2 */
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#define XMC4_IRQ_VADC_G1SR3 (XMC4_IRQ_FIRST + 25) /* 25: ADC Group 1, SR3 */
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#define XMC4_IRQ_VADC_G2SR0 (XMC4_IRQ_FIRST + 26) /* 26: ADC Group 2, SR0 */
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#define XMC4_IRQ_VADC_G2SR1 (XMC4_IRQ_FIRST + 27) /* 27: ADC Group 2, SR1 */
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#define XMC4_IRQ_VADC_G2SR2 (XMC4_IRQ_FIRST + 28) /* 28: ADC Group 2, SR2 */
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#define XMC4_IRQ_VADC_G2SR3 (XMC4_IRQ_FIRST + 29) /* 29: ADC Group 2, SR3 */
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#define XMC4_IRQ_VADC_G3SR0 (XMC4_IRQ_FIRST + 30) /* 30: ADC Group 3, SR0 */
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#define XMC4_IRQ_VADC_G3SR1 (XMC4_IRQ_FIRST + 31) /* 31: ADC Group 3, SR1 */
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#define XMC4_IRQ_VADC_G3SR2 (XMC4_IRQ_FIRST + 32) /* 32: ADC Group 3, SR2 */
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#define XMC4_IRQ_VADC_G3SR3 (XMC4_IRQ_FIRST + 33) /* 33: ADC Group 3, SR3 */
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#define XMC4_IRQ_DSD_SRM0 (XMC4_IRQ_FIRST + 34) /* 34: DSD Main, SRM0 */
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#define XMC4_IRQ_DSD_SRM1 (XMC4_IRQ_FIRST + 35) /* 35: DSD Main, SRM1 */
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#define XMC4_IRQ_DSD_SRM2 (XMC4_IRQ_FIRST + 36) /* 36: DSD Main, SRM2 */
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#define XMC4_IRQ_DSD_SRM3 (XMC4_IRQ_FIRST + 37) /* 37: DSD Main, SRM3 */
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#define XMC4_IRQ_DSD_SRA0 (XMC4_IRQ_FIRST + 38) /* 38: DSD Auxiliary, SRA0 */
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#define XMC4_IRQ_DSD_SRA1 (XMC4_IRQ_FIRST + 39) /* 39: DSD Auxiliary, SRA1 */
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#define XMC4_IRQ_DSD_SRA2 (XMC4_IRQ_FIRST + 40) /* 40: DSD Auxiliary, SRA2 */
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#define XMC4_IRQ_DSD_SRA3 (XMC4_IRQ_FIRST + 41) /* 41: DSD Auxiliary, SRA3 */
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#define XMC4_IRQ_DAC_SR0 (XMC4_IRQ_FIRST + 42) /* 42: DAC, SR0 */
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#define XMC4_IRQ_DAC_SR1 (XMC4_IRQ_FIRST + 43) /* 43: DAC, SR1 */
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#define XMC4_IRQ_CCU40_SR0 (XMC4_IRQ_FIRST + 44) /* 44: CCU4 Module 0, SR0 */
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#define XMC4_IRQ_CCU40_SR1 (XMC4_IRQ_FIRST + 45) /* 45: CCU4 Module 0, SR1 */
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#define XMC4_IRQ_CCU40_SR2 (XMC4_IRQ_FIRST + 46) /* 46: CCU4 Module 0, SR2 */
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#define XMC4_IRQ_CCU40_SR3 (XMC4_IRQ_FIRST + 47) /* 47: CCU4 Module 0, SR3 */
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#define XMC4_IRQ_CCU41_SR0 (XMC4_IRQ_FIRST + 48) /* 48: CCU4 Module 1, SR0 */
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#define XMC4_IRQ_CCU41_SR1 (XMC4_IRQ_FIRST + 49) /* 49: CCU4 Module 1, SR1 */
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#define XMC4_IRQ_CCU41_SR2 (XMC4_IRQ_FIRST + 50) /* 50: CCU4 Module 1, SR2 */
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#define XMC4_IRQ_CCU41_SR3 (XMC4_IRQ_FIRST + 51) /* 51: CCU4 Module 1, SR3 */
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#define XMC4_IRQ_CCU42_SR0 (XMC4_IRQ_FIRST + 52) /* 52: CCU4 Module 2, SR0 */
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#define XMC4_IRQ_CCU42_SR1 (XMC4_IRQ_FIRST + 53) /* 53: CCU4 Module 2, SR1 */
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#define XMC4_IRQ_CCU42_SR2 (XMC4_IRQ_FIRST + 54) /* 54: CCU4 Module 2, SR2 */
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#define XMC4_IRQ_CCU42_SR3 (XMC4_IRQ_FIRST + 55) /* 55: CCU4 Module 2, SR3 */
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#define XMC4_IRQ_CCU43_SR0 (XMC4_IRQ_FIRST + 56) /* 56: CCU4 Module 3, SR0 */
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#define XMC4_IRQ_CCU43_SR1 (XMC4_IRQ_FIRST + 57) /* 57: CCU4 Module 3, SR1 */
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#define XMC4_IRQ_CCU43_SR2 (XMC4_IRQ_FIRST + 58) /* 58: CCU4 Module 3, SR2 */
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#define XMC4_IRQ_CCU43_SR3 (XMC4_IRQ_FIRST + 59) /* 59: CCU4 Module 3, SR3 */
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#define XMC4_IRQ_CCU80_SR0 (XMC4_IRQ_FIRST + 60) /* 60: CCU8 Module 0, SR0 */
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#define XMC4_IRQ_CCU80_SR1 (XMC4_IRQ_FIRST + 61) /* 61: CCU8 Module 0, SR1 */
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#define XMC4_IRQ_CCU80_SR2 (XMC4_IRQ_FIRST + 62) /* 62: CCU8 Module 0, SR2 */
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#define XMC4_IRQ_CCU80_SR3 (XMC4_IRQ_FIRST + 63) /* 63: CCU8 Module 0, SR3 */
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#define XMC4_IRQ_CCU81_SR0 (XMC4_IRQ_FIRST + 64) /* 64: CCU8 Module 1, SR0 */
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#define XMC4_IRQ_CCU81_SR1 (XMC4_IRQ_FIRST + 65) /* 65: CCU8 Module 1, SR1 */
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#define XMC4_IRQ_CCU81_SR2 (XMC4_IRQ_FIRST + 66) /* 66: CCU8 Module 1, SR2 */
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#define XMC4_IRQ_CCU81_SR3 (XMC4_IRQ_FIRST + 67) /* 67: CCU8 Module 1, SR3 */
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#define XMC4_IRQ_POSIF0_SR0 (XMC4_IRQ_FIRST + 68) /* 68: POSIF Module 0, SR0 */
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#define XMC4_IRQ_POSIF0_SR1 (XMC4_IRQ_FIRST + 69) /* 69: POSIF Module 0, SR1 */
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#define XMC4_IRQ_POSIF1_SR0 (XMC4_IRQ_FIRST + 70) /* 70: POSIF Module 1, SR0 */
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#define XMC4_IRQ_POSIF1_SR1 (XMC4_IRQ_FIRST + 71) /* 71: POSIF Module 1, SR1 */
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#define XMC4_IRQ_RESVD072 (XMC4_IRQ_FIRST + 72) /* 72: Reserved */
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#define XMC4_IRQ_RESVD073 (XMC4_IRQ_FIRST + 73) /* 73: Reserved */
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#define XMC4_IRQ_RESVD074 (XMC4_IRQ_FIRST + 74) /* 74: Reserved */
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#define XMC4_IRQ_RESVD075 (XMC4_IRQ_FIRST + 75) /* 75: Reserved */
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#define XMC4_IRQ_CAN_SR0 (XMC4_IRQ_FIRST + 76) /* 76: MultiCAN, SR0 */
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#define XMC4_IRQ_CAN_SR1 (XMC4_IRQ_FIRST + 77) /* 77: MultiCAN, SR1 */
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#define XMC4_IRQ_CAN_SR2 (XMC4_IRQ_FIRST + 78) /* 78: MultiCAN, SR2 */
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#define XMC4_IRQ_CAN_SR3 (XMC4_IRQ_FIRST + 79) /* 79: MultiCAN, SR3 */
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#define XMC4_IRQ_CAN_SR4 (XMC4_IRQ_FIRST + 80) /* 80: MultiCAN, SR4 */
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#define XMC4_IRQ_CAN_SR5 (XMC4_IRQ_FIRST + 81) /* 81: MultiCAN, SR5 */
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#define XMC4_IRQ_CAN_SR6 (XMC4_IRQ_FIRST + 82) /* 82: MultiCAN, SR6 */
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#define XMC4_IRQ_CAN_SR7 (XMC4_IRQ_FIRST + 83) /* 83: MultiCAN, SR7 */
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#define XMC4_IRQ_USIC0_SR0 (XMC4_IRQ_FIRST + 84) /* 84: USIC0 Channel, SR0 */
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#define XMC4_IRQ_USIC0_SR1 (XMC4_IRQ_FIRST + 85) /* 85: USIC0 Channel, SR1 */
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#define XMC4_IRQ_USIC0_SR2 (XMC4_IRQ_FIRST + 86) /* 86: USIC0 Channel, SR2 */
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#define XMC4_IRQ_USIC0_SR3 (XMC4_IRQ_FIRST + 87) /* 87: USIC0 Channel, SR3 */
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#define XMC4_IRQ_USIC0_SR4 (XMC4_IRQ_FIRST + 88) /* 88: USIC0 Channel, SR4 */
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#define XMC4_IRQ_USIC0_SR5 (XMC4_IRQ_FIRST + 89) /* 89: USIC0 Channel, SR5 */
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#define XMC4_IRQ_USIC1_SR0 (XMC4_IRQ_FIRST + 90) /* 90: USIC1 Channel, SR0 */
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#define XMC4_IRQ_USIC1_SR1 (XMC4_IRQ_FIRST + 91) /* 91: USIC1 Channel, SR1 */
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#define XMC4_IRQ_USIC1_SR2 (XMC4_IRQ_FIRST + 92) /* 92: USIC1 Channel, SR2 */
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#define XMC4_IRQ_USIC1_SR3 (XMC4_IRQ_FIRST + 93) /* 93: USIC1 Channel, SR3 */
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#define XMC4_IRQ_USIC1_SR4 (XMC4_IRQ_FIRST + 94) /* 94: USIC1 Channel, SR4 */
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#define XMC4_IRQ_USIC1_SR5 (XMC4_IRQ_FIRST + 95) /* 95: USIC1 Channel, SR5 */
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#define XMC4_IRQ_USIC2_SR0 (XMC4_IRQ_FIRST + 96) /* 96: USIC2 Channel, SR0 */
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#define XMC4_IRQ_USIC2_SR1 (XMC4_IRQ_FIRST + 97) /* 97: USIC2 Channel, SR1 */
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#define XMC4_IRQ_USIC2_SR2 (XMC4_IRQ_FIRST + 98) /* 98: USIC2 Channel, SR2 */
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#define XMC4_IRQ_USIC2_SR3 (XMC4_IRQ_FIRST + 99) /* 99: USIC2 Channel, SR3 */
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#define XMC4_IRQ_USIC2_SR4 (XMC4_IRQ_FIRST + 100) /* 100: USIC2 Channel, SR4 */
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#define XMC4_IRQ_USIC2_SR5 (XMC4_IRQ_FIRST + 101) /* 101: USIC2 Channel, SR5 */
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#define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST + 102) /* 102: LEDTS0, SR0 */
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#define XMC4_IRQ_RESVD103 (XMC4_IRQ_FIRST + 103) /* 103: Reserved */
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#define XMC4_IRQ_FCR_SR0 (XMC4_IRQ_FIRST + 104) /* 102: FCE, SR0 */
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#define XMC4_IRQ_GPCMA0_SR0 (XMC4_IRQ_FIRST + 105) /* 105: GPDMA0, SR0 */
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#define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST + 106) /* 106: SDMMC, SR0 */
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#define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST + 107) /* 107: USB, SR0 */
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#define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST + 108) /* 108: Ethernet, module 0, SR0 */
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#define XMC4_IRQ_ECAT0_SR0 (XMC4_IRQ_FIRST + 109) /* 109: EtherCAT, module 0, SR0 */
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#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST + 110) /* 110: GPDMA1, SR0 */
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#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST + 111) /* 111: Reserved */
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#define XMC4_IRQ_NEXTINTS 112 /* 112 Non core IRQs */
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/* 128 vectors */
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#define XMC4_IRQ_NVECTORS (XMC4_IRQ_FIRST + XMC4_IRQ_NEXTINTS)
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/* GPIO IRQ interrupts -- To be provided */
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#define NR_IRQS XMC4_IRQ_NVECTORS
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#endif /* xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H */
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