36df84c843
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5145 42af7a65-404d-4744-a932-0658087f49c3
142 lines
8.5 KiB
C
142 lines
8.5 KiB
C
/************************************************************************************
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* arch/arm/src/kinetis/kinetis_usbdcd.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H
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#define __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define KINETIS_USBDCD_CONTROL_OFFSET 0x0000 /* Control Register */
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#define KINETIS_USBDCD_CLOCK_OFFSET 0x0004 /* Clock Register */
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#define KINETIS_USBDCD_STATUS_OFFSET 0x0008 /* Status Register */
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#define KINETIS_USBDCD_TIMER0_OFFSET 0x0010 /* TIMER0 Register */
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#define KINETIS_USBDCD_TIMER1_OFFSET 0x0014 /* TIMER1 Register */
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#define KINETIS_USBDCD_TIMER2_OFFSET 0x0018 /* TIMER2 Register */
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/* Register Addresses ***************************************************************/
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#define KINETIS_USBDCD_CONTROL (KINETIS_USBDCD_BASE+KINETIS_USBDCD_CONTROL_OFFSET)
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#define KINETIS_USBDCD_CLOCK (KINETIS_USBDCD_BASE+KINETIS_USBDCD_CLOCK_OFFSET)
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#define KINETIS_USBDCD_STATUS (KINETIS_USBDCD_BASE+KINETIS_USBDCD_STATUS_OFFSET)
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#define KINETIS_USBDCD_TIMER0 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER0_OFFSET)
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#define KINETIS_USBDCD_TIMER1 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER1_OFFSET)
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#define KINETIS_USBDCD_TIMER2 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET)
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/* Register Bit Definitions *********************************************************/
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/* Control Register */
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#define USBDCD_CONTROL_IACK (1 << 0) /* Bit 0: Interrupt Acknowledge */
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/* Bits 1-7: Reserved */
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#define USBDCD_CONTROL_IF (1 << 8) /* Bit 8: Interrupt Flag */
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/* Bits 9-15: Reserved */
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#define USBDCD_CONTROL_IE (1 << 16) /* Bit 16: Interrupt Enable */
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/* Bits 17-23: Reserved */
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#define USBDCD_CONTROL_START (1 << 24) /* Bit 24: Start Change Detection Sequence */
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#define USBDCD_CONTROL_SR (1 << 25) /* Bit 25: Software Reset */
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/* Bits 26-31: Reserved */
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/* Clock Register */
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#define USBDCD_CLOCK_UNIT (1 << 0) /* Bit 0: Unit of measurement encoding for Clock Speed */
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/* Bit 1: Reserved */
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#define USBDCD_CLOCK_SPEED_SHIFT (2) /* Bits 2-11: Value of Clock Speed */
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#define USBDCD_CLOCK_SPEED_MASK (0x3ff << USBDCD_CLOCK_SPEED_SHIFT)
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/* Bits 12-31: Reserved */
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/* Status Register */
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/* Bits 0-15: Reserved */
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#define USBDCD_STATUS_SEQ_RES_SHIFT (16) /* Bits 16-17: Charger Detection Sequence Results */
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#define USBDCD_STATUS_SEQ_RES_MASK (3 << USBDCD_STATUS_SEQ_RES_SHIFT)
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# define USBDCD_STATUS_SEQ_RES_NONE (0 << USBDCD_STATUS_SEQ_RES_SHIFT) /* No results */
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# define USBDCD_STATUS_SEQ_RES_STD (1 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Standard host */
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# define USBDCD_STATUS_SEQ_RES_CHGPORT (2 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Charging port */
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# define USBDCD_STATUS_SEQ_RES_DEDCTD (3 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Dedicated charge */
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#define USBDCD_STATUS_SEQ_STAT_SHIFT (18) /* Bits 18-19: Charger Detection Sequence Stat */
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#define USBDCD_STATUS_SEQ_STAT_MASK (3 << USBDCD_STATUS_SEQ_STAT_SHIFT)
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# define USBDCD_STATUS_SEQ_STAT_DISAB (0 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Not enabled or data pins not detected */
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# define USBDCD_STATUS_SEQ_STAT_DATPIN (1 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Data pin contact detection complete */
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# define USBDCD_STATUS_SEQ_STAT_CHGDET (2 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Charger detection is complete */
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# define USBDCD_STATUS_SEQ_STAT_CHGTYPE (3 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Charger type detection complete */
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#define USBDCD_STATUS_ERR (1 << 20) /* Bit 20: Error Flag */
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#define USBDCD_STATUS_TO (1 << 21) /* Bit 21: Timeout Flag */
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#define USBDCD_STATUS_ACTIVE (1 << 22) /* Bit 22: Active Status Indicator */
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/* Bits 23-31: Reserved */
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/* TIMER0 Register */
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#define USBDCD_TIMER0_TUNITCON_SHIFT (0) /* Bits 0-11: Unit Connection Timer Elapse (in ms) */
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#define USBDCD_TIMER0_TUNITCON_MASK (0xfff << USBDCD_TIMER0_TUNITCON_SHIFT)
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/* Bits 12-15: Reserved */
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#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16) /* Bits 16-25: Sequence Initiation Time */
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#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3ff << USBDCD_TIMER0_TSEQ_INIT_SHIFT)
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/* Bits 26-31: Reserved */
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/* TIMER1 Register */
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#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0) /* Bits 0-9: Time Period Comparator Enabled */
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#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3ff << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)
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/* Bits 10-15: Reserved */
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#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16) /* Bits 16-25: Time Period to Debounce D+ Signal */
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#define USBDCD_TIMER1_TDCD_DBNC__MASK (0x3ff << USBDCD_TIMER1_TDCD_DBNC_SHIFT)
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/* Bits 26-31: Reserved */
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/* TIMER2 Register */
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/* Bits 26-31: Reserved */
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#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT (16) /* Bits 16-25: Time Period Before Enabling D+ Pullup */
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#define USBDCD_TIMER2_TVDPSRC_CON_MASK (0x3ff << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)
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/* Bits 4-15: Reserved */
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#define USBDCD_TIMER2_CHECK_DM_SHIFT (0) /* Bits 0-3: Time Before Check of D- Line */
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#define USBDCD_TIMER2_CHECK_DM_MASK (15 << USBDCD_TIMER2_CHECK_DM_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H */
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